Tutorial rewrite draft 1
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AurelienUoU
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@ -18,10 +18,10 @@ rm -rf ${pwd_path}/results_OpenPithon
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cd ${pwd_path}/scripts
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# Replace keyword in config and architecture files
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perl rewrite_path_in_file -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file
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perl rewrite_path_in_file -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file
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perl rewrite_path_in_file -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file
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perl rewrite_path_in_file -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file
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perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file
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perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file
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perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file
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perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file
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# SRAM FPGA
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@ -1,22 +1,31 @@
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# Tutorial
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# FPGA flow
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This tutorial purpose it to clarify how to use:
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1. The full flow using fpga_flow.pl script
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2. Architecture customization
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This tutorial will help the user to understand how to use OpenFPGA flow.<br />
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During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations).
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Some keywords will be used during this tutorial:
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* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path
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## Running fpga_flow.pl
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### Folder organization
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A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
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OpenFPGA repository is organized as follow:
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* **abc**: open source synthesys tool
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* **ace2**: abc extension generating .act files
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* **vpr7_x2p**: sources of modified vpr
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* **yosys**: opensource synthesys tool
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* **fpga_flow**: scripts and dependencies to run the complete flow
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**Experiment**<br />
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cd fpga_flow<br />
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./tuto_fpga_flow.sh<br />
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## 1. FPGA flow
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**Explanation**<br />
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By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
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When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
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The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md)
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Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".<br />
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Few options are only in fpga_flow:
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* **-N**: number of LUT per CLB
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* **-K**: LUT size/ number of input
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* **-rpt <path>**: specifies wherever fpga_flow will write its report
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* **-ace_d <int_value>**: specifies inputs average probability of switching
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* **-multi_thread <int_value>**: specifies number of core to use
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* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist
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**
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The folder is organized as follow:
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* **arch**: contains architectures description files
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@ -35,7 +44,7 @@ fpga_flow.pl has dependencies which need to be configured. They are:
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* configuration file, which provides dependencies path and flow type
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* benchmark list file
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### a. Configuration file
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## Configuration file
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In this file paths have to be full path. Relative path could lead to errors.<br />
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The file is organized in 3 parts:
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@ -77,7 +86,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
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*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
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### b. Benchmark list
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## Benchmark list
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The benchmark folder contains 3 sub-folders:
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* **Blif**: contains .blif and .act of benchmarks
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@ -89,18 +98,3 @@ The benchmark list file can contain as many benchmarks as available in the same
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top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
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*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
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### c. Running fpga_flow.pl
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Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".<br />
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Few options are only in fpga_flow:
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* **-N**: number of LUT per CLB
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* **-K**: LUT size/ number of input
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* **-rpt <path>**: specifies wherever fpga_flow will write its report
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* **-ace_d <int_value>**: specifies inputs average probability of switching
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* **-multi_thread <int_value>**: specifies number of core to use
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* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist
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*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh*
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@ -0,0 +1,73 @@
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# OpenFPGA flow options
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Usage -> **fpga_flow *-options <value>* **<br />
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Mandatory options: <br />
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- -conf <file> : *specify the basic configuration files for fpga_flow*
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- -benchmark <file> : *the configuration file contains benchmark file names*
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- -rpt <file> : *CSV file consists of data*
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- -N <int> : *N-LUT/Matrix*
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Other Options:<br />
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## General
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- -matlab_rpt <data_name> : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script*
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- -I <int> : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen*
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- -K <int> : *K-LUT, mandatory when standard flow is chosen*
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- -M <int> : *M-Matrix, mandatory when mpack1 flow is chosen*
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- -power : *run power estimation oriented flow*
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- -black_box_ace: *run activity estimation with black box support. It increase the power.*
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- -remove_designs: *remove all the old results.*
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- -multi_thread <int>: *turn on the mutli-thread mode, specify the number of threads*
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- -multi_task <int>: *turn on the mutli-task mode*
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- -parse_results_only : *only parse the flow results and write CSV report.*
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- -debug : *debug mode*
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- -help : *print usage*
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## ODIN II
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- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
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- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
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- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow *
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## ABC
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- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.*
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- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.*
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## ACE
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- -ace_p <float> : *specify the default signal probablity of PIs in ACE2.*
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- -ace_d <float> : *specify the default signal density of PIs in ACE2.*
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## VPR - Original Version
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- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.*
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- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.*
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- -vpr_max_router_iteration <int> : *specify the max router iteration in VPR.*
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- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.*
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- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.*
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- -min_route_chan_width <float> : *turn on routing with <float>* min_route_chan_width.*
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- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.*
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## VPR - FPGA-X2P Extension
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- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE*
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- -vpr_fpga_x2p_signal_density_weight <float>: *specify the option signal_density_weight of VPR FPGA SPICE*
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- -vpr_fpga_x2p_sim_window_size <float>: *specify the option sim_window_size of VPR FPGA SPICE*
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- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization*
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## VPR - FPGA-SPICE Extension
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- -vpr_fpga_spice <task_file> : *turn on SPICE netlists print-out in VPR, specify a task file*
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- -vpr_fpga_spice_sim_mt_num <int>: *specify the option sim_mt_num of VPR FPGA SPICE*
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- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE*
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- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE*
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- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE*
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- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE*
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- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE*
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- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
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- -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
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## VPR - FPGA-Verilog Extension
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- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
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- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
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- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files*
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- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files*
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- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator*
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- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping*
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- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation*
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- -vpr_fpga_verilog_report_timing_rpt_path <path_to_generate_reports> : *Specify path for report timing*
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- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R*
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- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA*
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- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
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## VPR - FPGA-Bitstream Extension
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- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*
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# Tutorial introduction
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OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.<br />
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Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.<br /><br />
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These tutorials are organized as follow:
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* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md)
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* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md)
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* Architecture modification
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## Folder organization
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OpenFPGA repository is organized as follow:
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* **abc**: open source synthesys tool
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* **ace2**: abc extension generating .act files
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* **vpr7_x2p**: sources of modified vpr
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* **yosys**: opensource synthesys tool
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* **fpga_flow**: scripts and dependencies to run the complete flow
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## Tips and informations
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Some keywords will be used during this tutorial:
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* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path
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