Update tutorial, readme and docker
This commit is contained in:
AurelienUoU
parent
0da9e50b20
commit
e86c9b9bfc
|
|
@ -5,6 +5,4 @@ RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
|
|||
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
|
||||
|
||||
RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
|
||||
RUN cd OpenFPGA && make
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,8 @@ OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable
|
|||
|
||||
## Compilation
|
||||
|
||||
The different ways of compiling can be found in the **./compilation** folder.
|
||||
The different ways of compiling can be found in the **./compilation** folder.<br />
|
||||
Dependancies and help using docker can be found at **./tutorials/building.md**.
|
||||
|
||||
**Compilation steps:**
|
||||
1. Create a folder named build in OpenPFGA repository (mkdir build && cd build)
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh
|
||||
pause
|
||||
docker run -it --rm -v $PWD:/localfile -w="/localfile/vpr7_x2p/vpr" open_fpga bash
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
# How to build?
|
||||
|
||||
## Dependancies
|
||||
|
||||
OpenFPGA requires all the dependancies listed below:
|
||||
- autoconf
|
||||
- automake
|
||||
- bash
|
||||
- bison
|
||||
- build-essential
|
||||
- cmake (version 3.X at least)
|
||||
- ctags
|
||||
- curl
|
||||
- doxygen
|
||||
- flex
|
||||
- fontconfig
|
||||
- g++-8
|
||||
- gcc-8
|
||||
- g++-4.9
|
||||
- gcc-4.9
|
||||
- gdb
|
||||
- git
|
||||
- gperf
|
||||
- iverilog
|
||||
- libcairo2-dev
|
||||
- libevent-dev
|
||||
- libfontconfig1-dev
|
||||
- liblist-moreutils-perl
|
||||
- libncurses5-dev
|
||||
- libx11-dev
|
||||
- libxft-dev
|
||||
- libxml++2.6-dev
|
||||
- perl
|
||||
- python
|
||||
- texinfo
|
||||
- time
|
||||
- valgrind
|
||||
- zip
|
||||
- qt5-default
|
||||
|
||||
## Docker
|
||||
|
||||
If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands:
|
||||
- docker build . -t open_fpga
|
||||
- ./run_local.bat
|
||||
|
||||
## Building
|
||||
|
||||
To build the tool you have to be in OpenFPGA folder and do:
|
||||
- mkdir build && cd build
|
||||
- cmake ..
|
||||
- make OR make -j
|
||||
|
|
@ -29,7 +29,7 @@ fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in th
|
|||
* pro_blif.pl: rewrite a blif which has only 3 members in a .latch module
|
||||
* rewrite_path_in_file.pl: target a keyword in a file and replace it
|
||||
|
||||
*Any script provides a help if launch without argument*
|
||||
*Any script provides help if launch without argument*
|
||||
|
||||
fpga_flow.pl has dependencies which need to be configured. They are:
|
||||
* configuration file, which provides dependencies path and flow type
|
||||
|
|
@ -84,9 +84,9 @@ The benchmark folder contains 3 sub-folders:
|
|||
* **List**: contains all benchmark list files
|
||||
* **Verilog**: contains Verilog designs
|
||||
|
||||
Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**<br />
|
||||
The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:<br />
|
||||
top_module/*.v,<int_value>; where <int_value> is the number ofchannel/wire between each blocks.
|
||||
Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**<br />
|
||||
The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:<br />
|
||||
top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
|
||||
|
||||
*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
|
||||
|
||||
|
|
@ -101,8 +101,6 @@ Few options are only in fpga_flow:
|
|||
* **-multi_thread <int_value>**: specifies number of core to use
|
||||
* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist
|
||||
|
||||
*An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh*
|
||||
|
||||
|
||||
*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh*
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue