From e86c9b9bfc1dcf67cddecd5b0adc1f7839f6cd3b Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 9 Jul 2019 14:28:14 -0600 Subject: [PATCH] Update tutorial, readme and docker --- Dockerfile | 2 -- README.md | 3 ++- run_local.bat | 3 +-- tutorials/building.md | 52 +++++++++++++++++++++++++++++++++++++++++++ tutorials/tutorial.md | 12 +++++----- 5 files changed, 60 insertions(+), 12 deletions(-) create mode 100644 tutorials/building.md diff --git a/Dockerfile b/Dockerfile index c573dbbee..f4581d845 100755 --- a/Dockerfile +++ b/Dockerfile @@ -5,6 +5,4 @@ RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default -RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA -RUN cd OpenFPGA && make diff --git a/README.md b/README.md index aa61fff7c..e408da414 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,8 @@ OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable ## Compilation -The different ways of compiling can be found in the **./compilation** folder. +The different ways of compiling can be found in the **./compilation** folder.
+Dependancies and help using docker can be found at **./tutorials/building.md**. **Compilation steps:** 1. Create a folder named build in OpenPFGA repository (mkdir build && cd build) diff --git a/run_local.bat b/run_local.bat index 578f750ce..0a85df473 100755 --- a/run_local.bat +++ b/run_local.bat @@ -1,2 +1 @@ -docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh -pause +docker run -it --rm -v $PWD:/localfile -w="/localfile/vpr7_x2p/vpr" open_fpga bash diff --git a/tutorials/building.md b/tutorials/building.md new file mode 100644 index 000000000..f891378ad --- /dev/null +++ b/tutorials/building.md @@ -0,0 +1,52 @@ +# How to build? + +## Dependancies + +OpenFPGA requires all the dependancies listed below: +- autoconf +- automake +- bash +- bison +- build-essential +- cmake (version 3.X at least) +- ctags +- curl +- doxygen +- flex +- fontconfig +- g++-8 +- gcc-8 +- g++-4.9 +- gcc-4.9 +- gdb +- git +- gperf +- iverilog +- libcairo2-dev +- libevent-dev +- libfontconfig1-dev +- liblist-moreutils-perl +- libncurses5-dev +- libx11-dev +- libxft-dev +- libxml++2.6-dev +- perl +- python +- texinfo +- time +- valgrind +- zip +- qt5-default + +## Docker + +If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: +- docker build . -t open_fpga +- ./run_local.bat + +## Building + +To build the tool you have to be in OpenFPGA folder and do: +- mkdir build && cd build +- cmake .. +- make OR make -j diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index 9769f05de..7cc76342f 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -29,7 +29,7 @@ fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in th * pro_blif.pl: rewrite a blif which has only 3 members in a .latch module * rewrite_path_in_file.pl: target a keyword in a file and replace it -*Any script provides a help if launch without argument* +*Any script provides help if launch without argument* fpga_flow.pl has dependencies which need to be configured. They are: * configuration file, which provides dependencies path and flow type @@ -84,9 +84,9 @@ The benchmark folder contains 3 sub-folders: * **List**: contains all benchmark list files * **Verilog**: contains Verilog designs -Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**
-The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
-top_module/*.v,; where is the number ofchannel/wire between each blocks. +Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**
+The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
+top_module/*.v,; where is the number of channel/wire between each block. *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* @@ -101,8 +101,6 @@ Few options are only in fpga_flow: * **-multi_thread **: specifies number of core to use * **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist -*An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* - - +*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh*