From 20ce020eb6ad17338c9d73a298903d518bb25469 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 10:03:30 -0600 Subject: [PATCH] Tutorial rewrite draft 1 --- fpga_flow/tuto_fpga_flow.sh | 8 +- .../{tutorial.md => fpga_flow/how2use.md} | 56 +++++++------- tutorials/fpga_flow/options.md | 73 +++++++++++++++++++ tutorials/tutorial_index.md | 26 +++++++ 4 files changed, 128 insertions(+), 35 deletions(-) rename tutorials/{tutorial.md => fpga_flow/how2use.md} (78%) create mode 100644 tutorials/fpga_flow/options.md create mode 100644 tutorials/tutorial_index.md diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 7bfefb66d..c35e9cbf9 100644 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -18,10 +18,10 @@ rm -rf ${pwd_path}/results_OpenPithon cd ${pwd_path}/scripts # Replace keyword in config and architecture files -perl rewrite_path_in_file -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file -perl rewrite_path_in_file -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file -perl rewrite_path_in_file -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file -perl rewrite_path_in_file -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file +perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file +perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file +perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file +perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file # SRAM FPGA diff --git a/tutorials/tutorial.md b/tutorials/fpga_flow/how2use.md similarity index 78% rename from tutorials/tutorial.md rename to tutorials/fpga_flow/how2use.md index 7cc76342f..b0547bf48 100644 --- a/tutorials/tutorial.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,22 +1,31 @@ -# Tutorial +# FPGA flow -This tutorial purpose it to clarify how to use: -1. The full flow using fpga_flow.pl script -2. Architecture customization +This tutorial will help the user to understand how to use OpenFPGA flow.
+During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). -Some keywords will be used during this tutorial: -* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path +## Running fpga_flow.pl -### Folder organization +A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh. -OpenFPGA repository is organized as follow: -* **abc**: open source synthesys tool -* **ace2**: abc extension generating .act files -* **vpr7_x2p**: sources of modified vpr -* **yosys**: opensource synthesys tool -* **fpga_flow**: scripts and dependencies to run the complete flow +**Experiment**
+cd fpga_flow
+./tuto_fpga_flow.sh
-## 1. FPGA flow +**Explanation**
+By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
+When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md) + +Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
+Few options are only in fpga_flow: +* **-N**: number of LUT per CLB +* **-K**: LUT size/ number of input +* **-rpt **: specifies wherever fpga_flow will write its report +* **-ace_d **: specifies inputs average probability of switching +* **-multi_thread **: specifies number of core to use +* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist + +** The folder is organized as follow: * **arch**: contains architectures description files @@ -35,7 +44,7 @@ fpga_flow.pl has dependencies which need to be configured. They are: * configuration file, which provides dependencies path and flow type * benchmark list file -### a. Configuration file +## Configuration file In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: @@ -77,7 +86,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* -### b. Benchmark list +## Benchmark list The benchmark folder contains 3 sub-folders: * **Blif**: contains .blif and .act of benchmarks @@ -89,18 +98,3 @@ The benchmark list file can contain as many benchmarks as available in the same top_module/*.v,; where is the number of channel/wire between each block. *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* - -### c. Running fpga_flow.pl - -Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
-Few options are only in fpga_flow: -* **-N**: number of LUT per CLB -* **-K**: LUT size/ number of input -* **-rpt **: specifies wherever fpga_flow will write its report -* **-ace_d **: specifies inputs average probability of switching -* **-multi_thread **: specifies number of core to use -* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist - -*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* - - diff --git a/tutorials/fpga_flow/options.md b/tutorials/fpga_flow/options.md new file mode 100644 index 000000000..6f0b97366 --- /dev/null +++ b/tutorials/fpga_flow/options.md @@ -0,0 +1,73 @@ +# OpenFPGA flow options + +Usage -> **fpga_flow *-options * **
+Mandatory options:
+- -conf : *specify the basic configuration files for fpga_flow* +- -benchmark : *the configuration file contains benchmark file names* +- -rpt : *CSV file consists of data* +- -N : *N-LUT/Matrix* +Other Options:
+## General +- -matlab_rpt : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script* +- -I : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen* +- -K : *K-LUT, mandatory when standard flow is chosen* +- -M : *M-Matrix, mandatory when mpack1 flow is chosen* +- -power : *run power estimation oriented flow* +- -black_box_ace: *run activity estimation with black box support. It increase the power.* +- -remove_designs: *remove all the old results.* +- -multi_thread : *turn on the mutli-thread mode, specify the number of threads* +- -multi_task : *turn on the mutli-task mode* +- -parse_results_only : *only parse the flow results and write CSV report.* +- -debug : *debug mode* +- -help : *print usage* +## ODIN II +- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)* +- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen* +- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow * +## ABC +- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.* +- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.* +## ACE +- -ace_p : *specify the default signal probablity of PIs in ACE2.* +- -ace_d : *specify the default signal density of PIs in ACE2.* +## VPR - Original Version +- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.* +- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.* +- -vpr_max_router_iteration : *specify the max router iteration in VPR.* +- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.* +- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.* +- -min_route_chan_width : *turn on routing with * min_route_chan_width.* +- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.* +## VPR - FPGA-X2P Extension +- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE* +- -vpr_fpga_x2p_signal_density_weight : *specify the option signal_density_weight of VPR FPGA SPICE* +- -vpr_fpga_x2p_sim_window_size : *specify the option sim_window_size of VPR FPGA SPICE* +- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization* +## VPR - FPGA-SPICE Extension +- -vpr_fpga_spice : *turn on SPICE netlists print-out in VPR, specify a task file* +- -vpr_fpga_spice_sim_mt_num : *specify the option sim_mt_num of VPR FPGA SPICE* +- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE* +- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE* +- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE* +- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE* +- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE* +- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE* +- -vpr_fpga_spice_simulator_path : *Specify simulator path* +## VPR - FPGA-Verilog Extension +- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_dir : *provides the path where generated verilog files will be written* +- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files* +- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files* +- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files* +- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator* +- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping* +- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation* +- -vpr_fpga_verilog_report_timing_rpt_path : *Specify path for report timing* +- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R* +- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA* +- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_modelsim_autodeck : *turn on printing modelsim simulation script* +## VPR - FPGA-Bitstream Extension +- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator* diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md new file mode 100644 index 000000000..c6013d6dc --- /dev/null +++ b/tutorials/tutorial_index.md @@ -0,0 +1,26 @@ +# Tutorial introduction + +OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
+Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.

+These tutorials are organized as follow: +* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md) +* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md) +* Architecture modification + +## Folder organization + +OpenFPGA repository is organized as follow: +* **abc**: open source synthesys tool +* **ace2**: abc extension generating .act files +* **vpr7_x2p**: sources of modified vpr +* **yosys**: opensource synthesys tool +* **fpga_flow**: scripts and dependencies to run the complete flow + +## Tips and informations + +Some keywords will be used during this tutorial: +* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path + + + +