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adding member functions for circuit library

This commit is contained in:
tangxifan 2019-08-07 15:45:27 -06:00
parent 74da4ed51a
commit 38962c4607
5 changed files with 221 additions and 29 deletions
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1
libs/libvtrutil/src/vtr_geometry.h
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@ -49,6 +49,7 @@ template<class T>
class Point {
public: //Constructors
Point(T x_val, T y_val);
Point();
public: //Accessors

6
libs/libvtrutil/src/vtr_geometry.tpp
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@ -10,6 +10,12 @@ namespace vtr {
//pass
}
template<class T>
Point<T>::Point() {
//pass
}
template<class T>
T Point<T>::x() const {
return x_;

160
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp
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@ -33,6 +33,8 @@
* +-------------------------------------+
***********************************************************************/
#include "vtr_assert.h"
#include "circuit_library.h"
/************************************************************************
@ -44,15 +46,167 @@
***********************************************************************/
/************************************************************************
* Accessors
* Accessors : aggregates
***********************************************************************/
/* Aggregates */
CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const {
return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end());
}
/************************************************************************
* Accessors : Methods to find circuit model
***********************************************************************/
/* Find a circuit model by a given name and return its id */
CircuitModelId CircuitLibrary::get_circuit_model_id_by_name(const std::string& name) const {
CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID;
size_t num_found = 0;
for (circuit_model_string_iterator it = circuit_model_names_.begin();
it != circuit_model_names_.end();
it++) {
/* Bypass unmatched names */
if ( 0 != name.compare(*it) ) {
continue;
}
/* Find one and record it
* FIXME: I feel that we may have a better way in getting the CircuitModelId
*/
ret = CircuitModelId(it - circuit_model_names_.begin());
num_found++;
}
VTR_ASSERT((0 == num_found) || (1 == num_found));
return ret;
}
/* Get the CircuitModelId of a default circuit model with a given type */
CircuitModelId CircuitLibrary::get_default_circuit_model_id(const enum e_spice_model_type& type) const {
/* Default circuit model id is the first element by type in the fast look-up */
return circuit_model_lookup_[size_t(type)].front();
}
/************************************************************************
* Mutators
***********************************************************************/
/* Add a circuit model to the library, and return it Id */
CircuitModelId CircuitLibrary::add_circuit_model() {
/* Create a new id*/
CircuitModelId circuit_model_id = CircuitModelId(circuit_model_ids_.size());
/* Update the id list */
circuit_model_ids_.push_back(circuit_model_id);
/* Initialize other attributes */
/* Fundamental information */
circuit_model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES);
circuit_model_names_.emplace_back();
circuit_model_prefix_.emplace_back();
circuit_model_verilog_netlists_.emplace_back();
circuit_model_spice_netlists_.emplace_back();
circuit_model_is_default_.push_back(false);
/* Verilog generator options */
dump_structural_verilog_.push_back(false);
dump_explicit_port_map_.push_back(false);
/* Design technology information */
design_tech_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES);
power_gated_.push_back(false);
/* Buffer existence */
buffer_existence_.emplace_back();
buffer_circuit_model_names_.emplace_back();
buffer_circuit_model_ids_.emplace_back();
/* Pass-gate-related parameters */
pass_gate_logic_circuit_model_names_.emplace_back();
pass_gate_logic_circuit_model_ids_.emplace_back();
/* Port information */
port_types_.emplace_back();
port_sizes_.emplace_back();
port_prefix_.emplace_back();
port_lib_names_.emplace_back();
port_is_mode_select_.emplace_back();
port_is_global_.emplace_back();
port_is_reset_.emplace_back();
port_is_set_.emplace_back();
port_is_config_enable_.emplace_back();
port_is_prog_.emplace_back();
port_circuit_model_names_.emplace_back();
port_circuit_model_ids_.emplace_back();
port_inv_circuit_model_names_.emplace_back();
port_inv_circuit_model_ids_.emplace_back();
port_tri_state_maps_.emplace_back();
port_lut_frac_level_.emplace_back();
port_lut_output_masks_.emplace_back();
port_sram_orgz_.emplace_back();
/* Timing graphs */
edge_ids_.emplace_back();
port_in_edge_ids_.emplace_back();
port_out_edge_ids_.emplace_back();
edge_src_ports_.emplace_back();
edge_src_pin_ids_.emplace_back();
edge_sink_ports_.emplace_back();
edge_sink_pin_ids_.emplace_back();
edge_trise_.emplace_back();
edge_tfall_.emplace_back();
/* Delay information */
delay_types_.emplace_back();
delay_in_port_names_.emplace_back();
delay_out_port_names_.emplace_back();
delay_values_.emplace_back();
/* Buffer/Inverter-related parameters */
buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES);
buffer_location_maps_.emplace_back();
buffer_sizes_.push_back(-1);
buffer_is_tapered_.push_back(false);
buffer_num_levels_.push_back(-1);
buffer_f_per_stage_.push_back(-1);
/* Pass-gate-related parameters */
pass_gate_logic_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES);
pass_gate_logic_nmos_sizes_.push_back(-1);
pass_gate_logic_pmos_sizes_.push_back(-1);
/* Multiplexer-related parameters */
mux_structure_.push_back(NUM_CIRCUIT_MODEL_STRUCTURE_TYPES);
mux_num_levels_.push_back(-1);
mux_add_const_input_.push_back(false);
mux_const_input_values_.push_back(-1);
mux_use_local_encoder_.push_back(false);
mux_advanced_rram_design_.push_back(false);
/* LUT-related parameters */
lut_is_fracturable_.push_back(false);
/* RRAM-related design technology information */
rram_res_.emplace_back();
wprog_set_.emplace_back();
wprog_reset_.emplace_back();
/* Wire parameters */
wire_types_.push_back(NUM_WIRE_MODEL_TYPES);
wire_rc_.emplace_back();
wire_num_levels_.push_back(-1);
/* Invalidate fast look-up*/
return circuit_model_id;
}
/************************************************************************
* Internal Mutators
***********************************************************************/
/* Link the inv_circuit_model_id for each port of a circuit model.
* We search the inv_circuit_model_name in the CircuitLibrary and
* configure the port inv_circuit_model_id
*/
void CircuitLibrary::set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id) {
return;
}
/************************************************************************
* End of file : circuit_library.cpp
***********************************************************************/

65
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h
View File

@ -48,6 +48,7 @@
/* Header files should be included in a sequence */
/* Standard header files required go first */
#include "vtr_strong_id.h"
#include "vtr_geometry.h"
#include "vtr_vector.h"
#include "vtr_range.h"
@ -65,6 +66,12 @@ typedef vtr::StrongId<circuit_model_id_tag> CircuitModelId;
typedef vtr::StrongId<circuit_port_id_tag> CircuitPortId;
typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
/* Alias for open ids */
#define CIRCUIT_MODEL_OPEN_ID CircuitModelId(-1)
#define CIRCUIT_PORT_OPEN_ID CircuitPortId(-1)
#define CIRCUIT_EDGE_OPEN_ID CircuitEdgeId(-1)
/************************************************************************
* The class CircuitLibrary is a critical data structure for OpenFPGA
* It stores all the circuit-level details from XML architecture file
@ -82,6 +89,12 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
* 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated
* 7. is_default_: indicate if the circuit model is the default one among all those in the same type
*
* ------ Fast look-ups-----
* 1. circuit_model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users
* It classifies CircuitModelIds by their type and set the default model in the first element for each type.
* 2. circuit_model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users
* It classifies Ports by their types
*
* ------ Verilog generation options -----
* 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model
* 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model
@ -188,6 +201,7 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
class CircuitLibrary {
public: /* Types */
typedef vtr::vector<CircuitModelId, CircuitModelId>::const_iterator circuit_model_iterator;
typedef vtr::vector<CircuitModelId, std::string>::const_iterator circuit_model_string_iterator;
typedef vtr::vector<CircuitPortId, CircuitPortId>::const_iterator circuit_port_iterator;
typedef vtr::vector<CircuitEdgeId, CircuitEdgeId>::const_iterator circuit_edge_iterator;
/* Create range */
@ -199,20 +213,35 @@ class CircuitLibrary {
INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */
};
public: /* Constructors */
public: /* Accessors */
/* Aggregates */
public: /* Accessors: aggregates */
circuit_model_range circuit_models() const;
public: /* Accessors: Basic data query */
public: /* Accessors: Methods to find circuit model */
CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ;
CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const;
public: /* Mutators */
private: /* Internal functions */
CircuitModelId add_circuit_model();
public: /* Internal mutators */
void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id);
private: /* Internal validators */
private: /* Internal data */
/* Fundamental information */
vtr::vector<CircuitModelId, CircuitModelId> circuit_model_ids_;
vtr::vector<CircuitModelId, enum e_spice_model_type> circuit_model_types_;
vtr::vector<CircuitModelId, std::string> circuit_model_names_;
vtr::vector<CircuitModelId, std::string> circuit_model_prefix_;
vtr::vector<CircuitModelId, std::string> verilog_netlists_;
vtr::vector<CircuitModelId, std::string> spice_netlists_;
vtr::vector<CircuitModelId, bool> is_default_;
vtr::vector<CircuitModelId, std::string> circuit_model_verilog_netlists_;
vtr::vector<CircuitModelId, std::string> circuit_model_spice_netlists_;
vtr::vector<CircuitModelId, bool> circuit_model_is_default_;
/* fast look-up for circuit models to categorize by types
* [type][num_ids]
* Important: we force the default circuit model in the first element for each type
*/
typedef std::vector<std::vector<CircuitModelId>> CircuitModelLookup;
mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */
typedef std::vector<std::vector<std::vector<std::vector<CircuitPortId>>>> CircuitModelPortLookup;
mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_type][circuit_model_id][port_type][port_ids] */
/* Verilog generator options */
vtr::vector<CircuitModelId, bool> dump_structural_verilog_;
@ -224,12 +253,12 @@ class CircuitLibrary {
/* Buffer existence */
vtr::vector<CircuitModelId, std::vector<bool>> buffer_existence_;
vtr::vector<CircuitModelId, std::vector<std::string>> buffer_circuit_model_name_;
vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_circuit_model_id_;
vtr::vector<CircuitModelId, std::vector<std::string>> buffer_circuit_model_names_;
vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_circuit_model_ids_;
/* Pass-gate-related parameters */
vtr::vector<CircuitModelId, std::string> pass_gate_logic_circuit_model_name_;
vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_circuit_model_id_;
vtr::vector<CircuitModelId, std::string> pass_gate_logic_circuit_model_names_;
vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_circuit_model_ids_;
/* Port information */
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, enum e_spice_model_port_type>> port_types_;
@ -247,9 +276,9 @@ class CircuitLibrary {
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_circuit_model_ids_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_circuit_model_names_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_inv_circuit_model_ids_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_tri_state_map_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_tri_state_maps_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_lut_frac_level_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_lut_output_mask_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_lut_output_masks_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, enum e_sram_orgz>> port_sram_orgz_;
/* Timing graphs */
@ -294,17 +323,13 @@ class CircuitLibrary {
vtr::vector<CircuitModelId, bool> lut_is_fracturable_;
/* RRAM-related design technology information */
vtr::vector<CircuitModelId, float> rlrs_;
vtr::vector<CircuitModelId, float> rhrs_;
vtr::vector<CircuitModelId, float> wprog_set_nmos_;
vtr::vector<CircuitModelId, float> wprog_set_pmos_;
vtr::vector<CircuitModelId, float> wprog_reset_nmos_;
vtr::vector<CircuitModelId, float> wprog_reset_pmos_;
vtr::vector<CircuitModelId, vtr::Point<float>> rram_res_; /* x => R_LRS, y => R_HRS */
vtr::vector<CircuitModelId, vtr::Point<float>> wprog_set_; /* x => wprog_set_nmos, y=> wprog_set_pmos */
vtr::vector<CircuitModelId, vtr::Point<float>> wprog_reset_; /* x => wprog_reset_nmos, y=> wprog_reset_pmos */
/* Wire parameters */
vtr::vector<CircuitModelId, enum e_wire_model_type> wire_types_;
vtr::vector<CircuitModelId, float> wire_res_val_;
vtr::vector<CircuitModelId, float> wire_cap_val_;
vtr::vector<CircuitModelId, vtr::Point<float>> wire_rc_; /* x => wire_res_val, y=> wire_cap_val */
vtr::vector<CircuitModelId, size_t> wire_num_levels_;
};

18
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h
View File

@ -28,29 +28,34 @@ enum e_spice_model_type {
SPICE_MODEL_IOPAD,
SPICE_MODEL_INVBUF,
SPICE_MODEL_PASSGATE,
SPICE_MODEL_GATE
SPICE_MODEL_GATE,
NUM_CIRCUIT_MODEL_TYPES
};
enum e_spice_model_design_tech {
SPICE_MODEL_DESIGN_CMOS,
SPICE_MODEL_DESIGN_RRAM
SPICE_MODEL_DESIGN_RRAM,
NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES
};
enum e_spice_model_structure {
SPICE_MODEL_STRUCTURE_TREE,
SPICE_MODEL_STRUCTURE_ONELEVEL,
SPICE_MODEL_STRUCTURE_MULTILEVEL,
SPICE_MODEL_STRUCTURE_CROSSBAR
SPICE_MODEL_STRUCTURE_CROSSBAR,
NUM_CIRCUIT_MODEL_STRUCTURE_TYPES
};
enum e_spice_model_buffer_type {
SPICE_MODEL_BUF_INV,
SPICE_MODEL_BUF_BUF
SPICE_MODEL_BUF_BUF,
NUM_CIRCUIT_MODEL_BUF_TYPES
};
enum e_spice_model_pass_gate_logic_type {
SPICE_MODEL_PASS_GATE_TRANSMISSION,
SPICE_MODEL_PASS_GATE_TRANSISTOR
SPICE_MODEL_PASS_GATE_TRANSISTOR,
NUM_CIRCUIT_MODEL_PASS_GATE_TYPES
};
enum e_spice_model_gate_type {
@ -69,7 +74,8 @@ enum e_spice_trans_type {
enum e_wire_model_type {
WIRE_MODEL_PIE,
WIRE_MODEL_T
WIRE_MODEL_T,
NUM_WIRE_MODEL_TYPES,
};
enum e_spice_model_port_type {