add documentation for multi-mode configurable block support
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@ -19,6 +19,4 @@ Extended Architecture Description Language
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link_circuit_modules
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.. multimode_support
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@ -1,6 +1,6 @@
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Link circuit modules
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--------------------
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Each defined SPICE model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
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Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
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SRAM
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====
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@ -30,7 +30,7 @@ To link the defined circuit model of SRAM into the FPGA architecture description
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Example of a memory organization using memory decoders
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.. note:: Currently SPICE only supports standalone memory organization.
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.. note:: Currently circuit only supports standalone memory organization.
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.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
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@ -45,7 +45,7 @@ Switch Boxes
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=============
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Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
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To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
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To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
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Here is an example:
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@ -59,10 +59,10 @@ Here is an example:
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Connection Blocks
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================
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==================
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To link the defined SPICE model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
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Therefore, FPGA-SPICE requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
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To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
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Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
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Here is the example:
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@ -87,30 +87,98 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
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* circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
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Primitive Blocks inside Configurable Logic Blocks
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=================================================
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Primitive Blocks inside Multi-mode Configurable Logic Blocks
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=============================================================
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The architecture description employs a hierarchy of pb_types to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
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The architecture description employs a hierarchy of ``pb_types`` to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
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Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid circuit model, using the XML syntax ``circuit_model_name``.
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The ``circuit_model_name`` should match the given name of a ``circuit_model`` defined by users.
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.. code-block:: xml
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<pb_type name="clb" idle_mode_name="ble" physical_mode_name="ble">
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<pb_type name="ble">
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<pb_type name="lut" circuit_model_name="lut6">
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<pb_type name="ff" circuit_model_name="dff">
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<!-- Multi-mode BLE -->
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<pb_type name="ble" num_pb="10" physical_mode_name="ble_phy"/>
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<!-- Physical implementation of BLE shown in Fig. :ref:`` -->
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<mode name="ble_phy" disabled_in_packing="true"/>
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<!-- Define a 6-input LUT in BLE and link it to circuit model -->
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<pb_type name="flut6_phy" circuit_model_name="frac_lut6">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="lut5_out" num_pins="2"/>
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<output name="lut6_out" num_pins="1"/>
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</pb_type>
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<pb_type name="lut4_phy" circuit_model_name="lut4">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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</pb_type>
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<pb_type name="adder_phy" num_pb="2" circuit_model_name="adder">
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<input name="a" num_pins="1"/>
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<input name="b" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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</pb_type>
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<pb_type name="ff_phy" num_pb="2" circuit_model_name="dff">
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<input name="D" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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</pb_type>
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<interconnect>
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<mux input="lut.out ff.Q" output="ble.out" circuit_model_name="mux_1level">
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<!-- Routing multiplexers are omitted in this example. -->
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</interconnect>
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</pb_type>
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<interconnect>
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<mux input="ble.out clb.in" output="ble.in" circuit_model_name="mux_2level">
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</interconnect>
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</mode>
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<!-- Arithmetic mode of BLE shown in Fig. 2(b)-->
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<mode name="flut4_arithmetic"/>
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<pb_type name="flut4_arith" num_pb="4"/>
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<!-- Define a virtual 4-input LUT in BLE and link it to physical 6-input LUT defined at LINE 6 -->
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<pb_type name="lut4" mode_bits="01" physical_pb_type_name="flut6_phy">
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<!-- Define an input port and link it to its physical port defined at LINE 7 -->
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<input name="in" num_pins="4" physical_mode_pin="in[3:0]"/>
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<!-- Define an output port and link it to its physical port defined at LINE 8 -->
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<output name="out" num_pins="1" physical_mode_pin="lut4_out"/>
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</pb_type>
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<pb_type name="adder" num_pb="2" physical_pb_type_name="adder_phy">
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<input name="a" num_pins="1" physical_mode_pin="a"/>
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<input name="b" num_pins="1" physical_mode_pin="b"/>
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<input name="cin" num_pins="1" physical_mode_pin="cin"/>
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<output name="cout" num_pins="1" physical_mode_pin="cout"/>
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<output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
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</pb_type>
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<pb_type name="ff" num_pb="2" physical_pb_type_name="ff_phy">
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<input name="D" num_pins="1" physical_mode_pin="D"/>
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<output name="Q" num_pins="1" physical_mode_pin="Q"/>
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<clock name="clk" num_pins="1" physical_mode_pin="clk"/>
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</pb_type>
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<interconnect>
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<!-- Routing multiplexers are omitted in this example. Full details can be found in [21] -->
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</interconnect>
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</pb_type>
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</mode>
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<!-- More operating modes can be defined -->
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</pb_type>
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* **circuit_model_name:** should match a SPICE model defined under module_circuit_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case.
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* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one physical_mode should be specified for each multi-mode ``pb_type``.
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* **idle_mode_name:** tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks.
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* **idle_mode_name:** tell the name of the mode that the ``pb_type`` is configured to be by default. This is critical in building circuit netlists for unused logic blocks.
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* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of an FPGA.
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* **circuit_model_name:** should match a circuit model defined under ``module_circuit_models``. The ``circuit_model_name`` is mandatory for every leaf ``pb_type`` in a physical_mode ``pb_type``. For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
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* **mode_bits** specifies the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation.
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* **physical_pb_type_name** creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of leaf ``pb_type`` in physical mode.
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* **physical_pb_type_index_factor** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be multipled by the given factor.
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* **physical_pb_type_index_offset** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be shifted by the given factor.
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* **physical_mode_pin** creates the linke on ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match.
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* **physical_mode_pin_rotate_offset** aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
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.. note::
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It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description.
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.. note::
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Be careful in using ``physical_pb_type_index_factor``, ``physical_pb_type_index_offset`` and ``physical_mode_pin_rotate_offset``! Try to avoid using them unless for highly complex configuration blocks with very deep hierarchy.
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@ -1,4 +0,0 @@
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Modeling Physical Design of Multi-mode Configurable Logic Block Architectures
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=============================================================================
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Under construction
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@ -15,7 +15,7 @@ In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate p
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In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest.
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The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015`.
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The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
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FPGA-Verilog
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------------
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@ -24,7 +24,9 @@ On a second note, it is becoming more and more necessary to have fast access to
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This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user.
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In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section
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In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section.
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The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
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FPGA-Bitstream
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--------------
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@ -38,7 +38,7 @@ month={Sept},}
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@article{XTang_TCAS1_2016,
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title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}},
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author={Tang, Xifan and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
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author={X. Tang and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
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journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
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volume={63},
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number={4},
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@ -106,3 +106,16 @@ month={Sept},}
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address = {New York, NY, USA},
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keywords = {CAD, FPGA, architecture},
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}
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@ARTICLE{XTang_TVLSI_2019,
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author={X. Tang and E. Giacomin and G. D. Micheli and P. Gaillardon},
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journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
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title={{FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs}},
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year={2019},
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volume={27},
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number={3},
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pages={637-650},
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doi={10.1109/TVLSI.2018.2883923},
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ISSN={1063-8210},
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month={March},
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}
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