adding port mutators
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tangxifan
parent
ed4642a23f
commit
9f8c7a3fc7
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@ -117,11 +117,12 @@ CircuitModelId CircuitLibrary::add_circuit_model() {
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buffer_circuit_model_names_.emplace_back();
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buffer_circuit_model_ids_.emplace_back();
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/* Pass-gate-related parameters */
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/* Pass-gate-related parameters */
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pass_gate_logic_circuit_model_names_.emplace_back();
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pass_gate_logic_circuit_model_ids_.emplace_back();
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/* Port information */
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port_ids_.emplace_back();
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port_types_.emplace_back();
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port_sizes_.emplace_back();
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port_prefix_.emplace_back();
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@ -334,6 +335,77 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode
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return;
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}
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/* Set pass-gate logic information of a circuit model */
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void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) {
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/* validate the circuit_model_id */
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VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
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pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name;
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return;
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}
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/* Add a port to a circuit model */
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CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) {
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/* validate the circuit_model_id */
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VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
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/* Create a port id */
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CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size());
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/* Update the id list */
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port_ids_[circuit_model_id].push_back(circuit_port_id);
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/* Initialize other attributes */
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port_types_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES);
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port_sizes_[circuit_model_id].push_back(-1);
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port_prefix_[circuit_model_id].emplace_back();
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port_lib_names_[circuit_model_id].emplace_back();
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port_inv_prefix_[circuit_model_id].emplace_back();
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port_is_mode_select_[circuit_model_id].push_back(false);
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port_is_global_[circuit_model_id].push_back(false);
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port_is_reset_[circuit_model_id].push_back(false);
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port_is_set_[circuit_model_id].push_back(false);
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port_is_config_enable_[circuit_model_id].push_back(false);
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port_is_prog_[circuit_model_id].push_back(false);
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port_circuit_model_names_[circuit_model_id].emplace_back();
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port_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID);
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port_inv_circuit_model_names_[circuit_model_id].emplace_back();
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port_inv_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID);
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port_tri_state_maps_[circuit_model_id].emplace_back();
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port_lut_frac_level_[circuit_model_id].push_back(-1);
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port_lut_output_masks_[circuit_model_id].emplace_back();
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port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES);
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return circuit_port_id;
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}
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/* Set the type for a port of a circuit model */
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void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const enum e_spice_model_port_type& port_type) {
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/* validate the circuit_port_id */
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VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
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port_types_[circuit_model_id][circuit_port_id] = port_type;
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return;
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}
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/* Set the size for a port of a circuit model */
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void CircuitLibrary::set_port_sizes(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const size_t& port_size) {
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/* validate the circuit_port_id */
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VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
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port_sizes_[circuit_model_id][circuit_port_id] = port_size;
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return;
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}
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/* Set the prefix for a port of a circuit model */
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void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const std::string& port_prefix) {
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/* validate the circuit_port_id */
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VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
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port_prefix_[circuit_model_id][circuit_port_id] = port_prefix;
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return;
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}
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/************************************************************************
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* Internal Mutators
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***********************************************************************/
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@ -411,6 +483,12 @@ bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_
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return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] );
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}
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bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const {
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/* validate the circuit_model_id */
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VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
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return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] );
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}
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/* Invalidators */
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/* Empty fast lookup for circuit_models*/
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void CircuitLibrary::invalidate_circuit_model_lookup() const {
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@ -117,25 +117,26 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
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* 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic
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*
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* ------ Port information ------
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* 1. port_types_: types of ports belonging to a circuit model
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* 2. port_sizes_: width of ports belonging to a circuit model
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* 3. port_prefix_: prefix of a port when instance of a circuit model
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* 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled
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* 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port
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* 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model
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* 7. port_is_global: specify if this port is a global signal shared by other circuit model
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* 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches
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* 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches
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* 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches
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* 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches
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* 12. port_circuit_model_name: the name of circuit model linked to the port
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* 13. port_circuit_model_ids_: the Id of circuit model linked to the port
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* 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port
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* 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port
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* 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port
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* 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
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* 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
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* 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains
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* 1. port_ids_: unique id of ports belonging to a circuit model
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* 2. port_types_: types of ports belonging to a circuit model
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* 3. port_sizes_: width of ports belonging to a circuit model
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* 4. port_prefix_: prefix of a port when instance of a circuit model
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* 5. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled
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* 6. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port
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* 7. port_is_mode_select: specify if this port is used to select operating modes of the circuit model
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* 8. port_is_global: specify if this port is a global signal shared by other circuit model
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* 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches
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* 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches
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* 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches
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* 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches
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* 13. port_circuit_model_name: the name of circuit model linked to the port
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* 14. port_circuit_model_ids_: the Id of circuit model linked to the port
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* 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port
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* 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port
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* 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port
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* 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
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* 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
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* 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains
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*
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* ------ Delay information ------
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* 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge
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@ -223,21 +224,43 @@ class CircuitLibrary {
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CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const;
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public: /* Public Mutators */
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CircuitModelId add_circuit_model();
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/* Fundamental information */
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void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type);
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void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name);
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void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix);
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void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist);
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void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist);
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void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default);
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/* Verilog generator options */
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void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog);
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void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map);
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/* Design technology information */
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void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type);
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void set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated);
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void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name);
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/* Buffer existence */
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void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id,
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const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id,
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const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id,
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const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id,
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const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id,
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const bool& existence, const std::string& circuit_model_name);
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/* Pass-gate-related parameters */
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void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name);
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/* Port information */
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CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id);
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void set_port_types(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const enum e_spice_model_port_type& port_type);
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void set_port_sizes(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const size_t& port_size);
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void set_port_prefix(const CircuitModelId& circuit_model_id,
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const CircuitPortId& circuit_port_id,
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const std::string& port_prefix);
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public: /* Internal mutators: link circuit_models */
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void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name);
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void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id);
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@ -246,6 +269,7 @@ class CircuitLibrary {
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private: /* Internal invalidators/validators */
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/* Validators */
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bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const;
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bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
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/* Invalidators */
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void invalidate_circuit_model_lookup() const;
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void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const;
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@ -286,6 +310,7 @@ class CircuitLibrary {
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vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_circuit_model_ids_;
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/* Port information */
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitPortId>> port_ids_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, enum e_spice_model_port_type>> port_types_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_sizes_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_prefix_;
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@ -87,7 +87,8 @@ enum e_spice_model_port_type {
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SPICE_MODEL_PORT_BL,
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SPICE_MODEL_PORT_BLB,
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SPICE_MODEL_PORT_WL,
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SPICE_MODEL_PORT_WLB
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SPICE_MODEL_PORT_WLB,
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NUM_CIRCUIT_MODEL_PORT_TYPES
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};
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/* For process corner */
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@ -102,7 +103,8 @@ enum e_sram_orgz {
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SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */
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SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */
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SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */
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SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */
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SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */
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NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES
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};
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enum e_spice_accuracy_type {
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