From 9f8c7a3fc74e86142f199f65ad883a2ecb6a8593 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 17:47:39 -0600 Subject: [PATCH] adding port mutators --- .../fpga_spice_include/circuit_library.cpp | 80 ++++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 73 +++++++++++------ .../SRC/fpga_spice_include/spice_types.h | 6 +- 3 files changed, 132 insertions(+), 27 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 2a6e32756..3bc99a079 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -117,11 +117,12 @@ CircuitModelId CircuitLibrary::add_circuit_model() { buffer_circuit_model_names_.emplace_back(); buffer_circuit_model_ids_.emplace_back(); - /* Pass-gate-related parameters */ + /* Pass-gate-related parameters */ pass_gate_logic_circuit_model_names_.emplace_back(); pass_gate_logic_circuit_model_ids_.emplace_back(); /* Port information */ + port_ids_.emplace_back(); port_types_.emplace_back(); port_sizes_.emplace_back(); port_prefix_.emplace_back(); @@ -334,6 +335,77 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode return; } +/* Set pass-gate logic information of a circuit model */ +void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name; + return; +} + +/* Add a port to a circuit model */ +CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Create a port id */ + CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size()); + /* Update the id list */ + port_ids_[circuit_model_id].push_back(circuit_port_id); + + /* Initialize other attributes */ + port_types_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); + port_sizes_[circuit_model_id].push_back(-1); + port_prefix_[circuit_model_id].emplace_back(); + port_lib_names_[circuit_model_id].emplace_back(); + port_inv_prefix_[circuit_model_id].emplace_back(); + port_is_mode_select_[circuit_model_id].push_back(false); + port_is_global_[circuit_model_id].push_back(false); + port_is_reset_[circuit_model_id].push_back(false); + port_is_set_[circuit_model_id].push_back(false); + port_is_config_enable_[circuit_model_id].push_back(false); + port_is_prog_[circuit_model_id].push_back(false); + port_circuit_model_names_[circuit_model_id].emplace_back(); + port_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); + port_inv_circuit_model_names_[circuit_model_id].emplace_back(); + port_inv_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); + port_tri_state_maps_[circuit_model_id].emplace_back(); + port_lut_frac_level_[circuit_model_id].push_back(-1); + port_lut_output_masks_[circuit_model_id].emplace_back(); + port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + + return circuit_port_id; +} + +/* Set the type for a port of a circuit model */ +void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_types_[circuit_model_id][circuit_port_id] = port_type; + return; +} + +/* Set the size for a port of a circuit model */ +void CircuitLibrary::set_port_sizes(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_sizes_[circuit_model_id][circuit_port_id] = port_size; + return; +} + +/* Set the prefix for a port of a circuit model */ +void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& port_prefix) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_prefix_[circuit_model_id][circuit_port_id] = port_prefix; + return; +} + /************************************************************************ * Internal Mutators ***********************************************************************/ @@ -411,6 +483,12 @@ bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_ return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] ); } +bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); +} + /* Invalidators */ /* Empty fast lookup for circuit_models*/ void CircuitLibrary::invalidate_circuit_model_lookup() const { diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b6a5464b4..4a0e791a1 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -117,25 +117,26 @@ typedef vtr::StrongId CircuitEdgeId; * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic * * ------ Port information ------ - * 1. port_types_: types of ports belonging to a circuit model - * 2. port_sizes_: width of ports belonging to a circuit model - * 3. port_prefix_: prefix of a port when instance of a circuit model - * 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled - * 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port - * 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model - * 7. port_is_global: specify if this port is a global signal shared by other circuit model - * 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches - * 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches - * 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 12. port_circuit_model_name: the name of circuit model linked to the port - * 13. port_circuit_model_ids_: the Id of circuit model linked to the port - * 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port - * 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port - * 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 1. port_ids_: unique id of ports belonging to a circuit model + * 2. port_types_: types of ports belonging to a circuit model + * 3. port_sizes_: width of ports belonging to a circuit model + * 4. port_prefix_: prefix of a port when instance of a circuit model + * 5. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled + * 6. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port + * 7. port_is_mode_select: specify if this port is used to select operating modes of the circuit model + * 8. port_is_global: specify if this port is a global signal shared by other circuit model + * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches + * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches + * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches + * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 13. port_circuit_model_name: the name of circuit model linked to the port + * 14. port_circuit_model_ids_: the Id of circuit model linked to the port + * 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -223,21 +224,43 @@ class CircuitLibrary { CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; public: /* Public Mutators */ CircuitModelId add_circuit_model(); + /* Fundamental information */ void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); + /* Verilog generator options */ void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); + /* Design technology information */ void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); void set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated); - void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + /* Buffer existence */ + void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + /* Pass-gate-related parameters */ + void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); + /* Port information */ + CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); + void set_port_types(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type); + void set_port_sizes(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size); + void set_port_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& port_prefix); public: /* Internal mutators: link circuit_models */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); @@ -246,6 +269,7 @@ class CircuitLibrary { private: /* Internal invalidators/validators */ /* Validators */ bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; + bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; /* Invalidators */ void invalidate_circuit_model_lookup() const; void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; @@ -286,6 +310,7 @@ class CircuitLibrary { vtr::vector pass_gate_logic_circuit_model_ids_; /* Port information */ + vtr::vector> port_ids_; vtr::vector> port_types_; vtr::vector> port_sizes_; vtr::vector> port_prefix_; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index d3ad32ae7..7711285a2 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -87,7 +87,8 @@ enum e_spice_model_port_type { SPICE_MODEL_PORT_BL, SPICE_MODEL_PORT_BLB, SPICE_MODEL_PORT_WL, - SPICE_MODEL_PORT_WLB + SPICE_MODEL_PORT_WLB, + NUM_CIRCUIT_MODEL_PORT_TYPES }; /* For process corner */ @@ -102,7 +103,8 @@ enum e_sram_orgz { SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ - SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ + SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ + NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES }; enum e_spice_accuracy_type {