tangxifan
|
c4d3e7c50c
|
[Doc] Update documentation for the new XML syntax in simulation settings
|
2021-01-15 12:30:26 -07:00 |
|
tangxifan
|
0c808bec41
|
[Doc] Add clarification for defining multi-bit global tile ports
|
2021-01-09 20:00:16 -07:00 |
|
tangxifan
|
2324edc522
|
[Doc] Update documentation for upgraded tile annotation
|
2021-01-09 18:55:16 -07:00 |
|
tangxifan
|
226f6b8d6d
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
Lalit Sharma
|
0e7c04878c
|
Merge remote-tracking branch 'origin/master' into replace_yosys
Merging latest changes from master.
|
2020-12-14 20:57:26 -08:00 |
|
tangxifan
|
024bc17b84
|
[Doc] Bug fix on the incompatible sphinx bibtex version. Constrain to the right version.
|
2020-12-14 09:37:45 -07:00 |
|
Lalit Sharma
|
3ccd6b80dd
|
Updating compile.rst file with updated compilation steps
|
2020-12-13 21:04:10 -08:00 |
|
tangxifan
|
406edeec89
|
[Doc] Typo fix
|
2020-12-04 15:07:02 -07:00 |
|
tangxifan
|
4fe190fa7e
|
[Doc] Bug fix in LUT circuit model documentation
|
2020-12-04 14:44:27 -07:00 |
|
tangxifan
|
8350b0f911
|
[Doc] Update documentation about default value definition in tile annotation
|
2020-12-02 17:08:34 -07:00 |
|
tangxifan
|
cc0114459a
|
[Doc] Enrich examples for LUT circuit models
|
2020-11-26 13:03:12 -07:00 |
|
tangxifan
|
62e804215b
|
[Doc] Add svg figures for LUT examples
|
2020-11-26 12:35:39 -07:00 |
|
tangxifan
|
b857135f4e
|
[Doc] Add clarification about which cells are applicable for signal initialization
|
2020-11-23 15:19:15 -07:00 |
|
tangxifan
|
2b9a97729e
|
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
|
2020-11-23 15:09:47 -07:00 |
|
tangxifan
|
fd0e6814ea
|
[Doc] Update documentation about the pre-processing flags
|
2020-11-22 20:33:15 -07:00 |
|
tangxifan
|
f6126d1ed6
|
[Doc] Add illustrative example to diff between global ports definitions
|
2020-11-12 09:24:39 -07:00 |
|
tangxifan
|
bc43c876b0
|
[Doc] Update documentation for the rules in global port definition for tile ports
|
2020-11-11 14:10:11 -07:00 |
|
tangxifan
|
2c269c532a
|
[Doc] Update doc for the global port definition using physical tile port
|
2020-11-10 20:48:28 -07:00 |
|
tangxifan
|
056b7c0c79
|
[Doc] Update documentation about CCFF circuit model examples
|
2020-11-06 12:22:22 -07:00 |
|
tangxifan
|
55b14fa6b4
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-11-06 10:11:38 -07:00 |
|
tangxifan
|
849ecc7fc0
|
[Doc] Add notes for using the is_data_io syntax
|
2020-11-05 09:30:19 -07:00 |
|
tangxifan
|
9bce2f3818
|
[Doc] Update documentation for new XML syntax "is_data_io"
|
2020-11-05 09:28:46 -07:00 |
|
tangxifan
|
032cbfb8b2
|
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
|
tangxifan
|
be7f7592ae
|
[Doc] Update documentation about don't care bit in frame address
|
2020-10-30 22:13:28 -06:00 |
|
tangxifan
|
7e940980e1
|
[Doc] Update documentation about configuration regions for frame-based protocol
|
2020-10-30 21:52:01 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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cd0d3dd798
|
Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
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2020-10-29 18:39:44 -06:00 |
|
tangxifan
|
c2c384e24b
|
[Doc] update documentation about memory bank definition
|
2020-10-29 17:04:25 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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ff9c17cba8
|
Merge pull request #111 from LNIS-Projects/dev
Bug fix in tutorial due to renamed regression tests
|
2020-10-28 09:40:28 -06:00 |
|
tangxifan
|
efb0162e3f
|
[Doc] Bug fix in tutorial due to renamed regression tests
|
2020-10-28 08:58:19 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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16128f0905
|
Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
|
2020-10-12 13:47:40 -06:00 |
|
tangxifan
|
3aeea724de
|
[Documentation] Update for new options in fpga-verilog
|
2020-10-12 12:36:24 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
5efe1ae77d
|
Merge pull request #106 from LNIS-Projects/dev
Documentation update
|
2020-10-10 23:16:37 -06:00 |
|
tangxifan
|
ccaa697e5a
|
[Documentation] Add links to technical features to examples
|
2020-10-10 22:40:37 -06:00 |
Andrew Lukefahr
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00295a003f
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Docs: Updated note to enable VPR's GUI
|
2020-10-06 20:47:43 -04:00 |
|
tangxifan
|
800931c840
|
[Documentation] Add configuration protocol to technical highlights
|
2020-10-06 12:16:15 -06:00 |
|
tangxifan
|
56ab63d939
|
[Documentation] Fix format in table
|
2020-10-06 12:02:15 -06:00 |
|
tangxifan
|
c8339fc473
|
[Documentation] Typo fix
|
2020-10-06 12:00:30 -06:00 |
|
tangxifan
|
113708c68f
|
[Documentation] Reorganization the overview part by adding technical highlights
|
2020-10-06 11:56:10 -06:00 |
|
tangxifan
|
02e21d115b
|
[Documentation] Update 3-rd party tool version requirements
|
2020-10-06 10:00:12 -06:00 |
|
tangxifan
|
67300af987
|
[Documentation] Update motivation with new set of figures
|
2020-09-29 16:52:16 -06:00 |
|
tangxifan
|
6817c045c2
|
[Documentation] Update tutorial about tooling
|
2020-09-29 16:24:52 -06:00 |
|
tangxifan
|
639d57016b
|
[Documentation] Update documentation about the multi-region configuration
|
2020-09-29 15:55:42 -06:00 |
|
tangxifan
|
462886fb5f
|
[Documentation] Update documentation for the multiple region support on configuration chain
|
2020-09-29 14:02:03 -06:00 |
|
tangxifan
|
94a1324f05
|
[Documentation] Remove deprecated XML syntax
|
2020-09-26 14:31:57 -06:00 |
|
tangxifan
|
f57fd273af
|
[Documentation] Update documentation for smart fast configuration
|
2020-09-23 21:28:06 -06:00 |
|
tangxifan
|
3d234d840b
|
[Documentation] Update documentation for the edge triggered attribute
|
2020-09-23 20:31:11 -06:00 |
|
tangxifan
|
7a2502ddf9
|
[documentation] add more guidelines about the vpr-openfpga architecture annotation
|
2020-09-02 22:47:14 -06:00 |
|
tangxifan
|
b5251ce5af
|
[documentation] update motivation figure and layout licenses
|
2020-09-01 11:07:50 -06:00 |
|
tangxifan
|
ac8e937a50
|
[Documentation] Update for default circuit model rules
|
2020-08-23 14:08:38 -06:00 |
|
tangxifan
|
fb5a5a2448
|
[documentation] remove the limitation on through channels
|
2020-08-19 20:12:49 -06:00 |
|
tangxifan
|
47f15729ad
|
update doc about the limitation on using tileable routing
|
2020-08-19 18:37:28 -06:00 |
|
tangxifan
|
d6d17675e2
|
update docoumentation about the constraints when using tileable rr_graph generator
|
2020-08-19 18:01:32 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
53f87f44b4
|
update documentation for the multi-port support in physical pb_pin
|
2020-08-18 12:44:38 -06:00 |
|
tangxifan
|
cfd035bf8f
|
update tutorials about the verilog-to-verification
|
2020-08-17 14:33:51 -06:00 |
|
tangxifan
|
f773491f87
|
update documentation to sync with the new fabric bitstream format
|
2020-07-27 16:37:10 -06:00 |
|
tangxifan
|
50ac78f906
|
update documentation for the split fabric bitstream
|
2020-07-27 14:26:02 -06:00 |
|
tangxifan
|
fcd8a3cf4d
|
update doc format
|
2020-07-27 13:59:36 -06:00 |
|
tangxifan
|
a24754611c
|
update documentation about the 'width' syntax of fabric dependent bitstream
|
2020-07-27 13:56:57 -06:00 |
|
Xifan Tang
|
aef1d7ba63
|
bug fix in doc about showing example fabric bitstream
|
2020-07-26 22:50:06 -06:00 |
|
tangxifan
|
872a35fc60
|
update doc to fix format problem; add frame_view to doc
|
2020-07-26 22:39:33 -06:00 |
|
tangxifan
|
1f39540672
|
update documentation about fabric bitstream file formats
|
2020-07-26 21:38:33 -06:00 |
|
tangxifan
|
c3fd817bae
|
update documentation about new XML syntax max width
|
2020-07-24 16:33:01 -06:00 |
|
tangxifan
|
c26c268dcd
|
update documentation on fast configuration support for configuration chain
|
2020-07-15 13:55:32 -06:00 |
|
tangxifan
|
862d71f57a
|
remove obselete vpr7 XML syntax from documentation
|
2020-07-15 11:13:47 -06:00 |
|
tangxifan
|
cb0df2c1c6
|
update doc about technology binding between circuit library and device library
|
2020-07-15 11:05:33 -06:00 |
|
tangxifan
|
65dfc545c1
|
update documentation for fabric key
|
2020-07-07 10:28:29 -06:00 |
|
tangxifan
|
7615db2be6
|
update documentation for the new fabric key rules
|
2020-07-06 16:44:21 -06:00 |
|
tangxifan
|
ece262f544
|
remove debug mode in compilation guidelines as we can use release in default now
|
2020-07-04 19:19:06 -06:00 |
|
tangxifan
|
933801cfa7
|
update documentation about alias support in fabric key
|
2020-06-27 15:04:04 -06:00 |
|
tangxifan
|
db5397fa75
|
update tutorial about architecture to synchronize with latest file organization
|
2020-06-24 10:51:26 -06:00 |
|
tangxifan
|
161d1474c1
|
keep tutorial updated to the latest regression test organization
|
2020-06-24 10:36:08 -06:00 |
|
tangxifan
|
8b8d92d186
|
update documentation for new bitstream file format
|
2020-06-20 18:59:45 -06:00 |
|
tangxifan
|
91b072d7c5
|
documentation update on the bitstream file format to synchronize with the latest codes
|
2020-06-17 11:56:40 -06:00 |
|
tangxifan
|
ba38120093
|
add documentation for fabric key and reorganize command references
|
2020-06-12 16:15:16 -06:00 |
|
tangxifan
|
1a006f2ddb
|
update documentation for separated XML files
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
b9dd47d465
|
update documentation about memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c00653961e
|
minor format fix in documentation
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0931eccbf6
|
update documentation for the fast configuration options
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fe2ba7d50a
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
de07712a3a
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
1150b903a5
|
add quick start tutorial for architecture modeling
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
339bf87c43
|
add missing file
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
aa77ee9af6
|
add tutorial for full testbench run
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
35536ee594
|
renaming design flows in documentation
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
011ce5cdf6
|
minor fix on the documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f079c61bd3
|
re organize tutorials
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
dcce782a46
|
update documentation about Verilog testbenches
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c5a3e44e61
|
Update Verilog fabric netlist documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
cae7fe0fed
|
minor fix on the manual subtree
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c27d77a418
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f6895fcc14
|
update documentation for new options of Verilog testbench writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
c2a81c76e1
|
update doc for new options
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
f4dd882f0f
|
documentation updated for new command
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
df9cf32b49
|
update documenation for configuration chain writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
a41c8dbcb3
|
change to use default sphinx build version
|
2020-06-11 19:31:06 -06:00 |
|
Xifan Tang
|
24934aff86
|
update documentation on the depth option for fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
752470c2da
|
update documentation on write hierarchy command and options
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
ac378febef
|
update doc about time units in SDC generator
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
d18e924a89
|
Update documentation on new fpga_sdc option
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
ecdbdcb592
|
update documentation on new SDC options
|
2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
|
52adebacfb
|
update doc for file options in openfpga bitstream
|
2020-04-21 14:40:53 -06:00 |
|
Xifan Tang
|
b4542ea34b
|
minor fix on doc about the global and general purpose port
|
2020-04-09 17:10:04 -06:00 |
|
Xifan Tang
|
d99776b260
|
update documentation on the global I/O ports
|
2020-04-08 18:18:53 -06:00 |
|
Xifan Tang
|
b9ade3fcb6
|
documentation update to introduce new features in script mode of OpenFPGA shell
|
2020-04-08 14:13:28 -06:00 |
|
Xifan Tang
|
55e68896d6
|
doc update for the support on std cell MUX2 and examples
|
2020-04-07 12:01:13 -06:00 |
|
Xifan Tang
|
7a4137fdcf
|
doc update for packable XML syntax in VPR
|
2020-04-06 18:37:05 -06:00 |
|
Xifan Tang
|
1a3a748dd2
|
update documentation with the support on spypads and global I/O ports
|
2020-04-05 20:12:28 -06:00 |
|
Xifan Tang
|
6ce0fe4ef2
|
doc update for FPGA-bitstream to better motivate the different types of bitstream
|
2020-04-01 12:57:28 -06:00 |
|
Xifan Tang
|
fd8248d9dd
|
update documentation: the addon syntax on VPR and configuration protocols
|
2020-04-01 12:35:52 -06:00 |
|
tangxifan
|
78964ce71c
|
update documentation on the through channel
|
2020-03-27 11:34:39 -06:00 |
|
Xifan Tang
|
b4221e94bb
|
add documentation on the tileable routing and thru channel support
|
2020-03-25 16:52:42 -06:00 |
|
Xifan Tang
|
cb6afea07c
|
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
|
2020-03-25 16:00:25 -06:00 |
|
Xifan Tang
|
3a74fb7a04
|
update documentation for the new options
|
2020-03-25 15:23:21 -06:00 |
|
Xifan Tang
|
7e3a8e5794
|
typo fixed in fpga-bitstream documentation
|
2020-03-22 16:27:12 -06:00 |
|
Xifan Tang
|
75dfe6a045
|
update documentation for write_gsb_to_xml functionality
|
2020-03-22 16:21:35 -06:00 |
|
tangxifan
|
1d766d2a70
|
minor format fix on documentation
|
2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
|
b941ac8a4a
|
remove deprecated options
|
2020-03-10 20:58:00 -06:00 |
|
Xifan Tang
|
8037d1ad93
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-03-10 20:55:02 -06:00 |
|
Xifan Tang
|
9f743f7f4e
|
add openfpga shell documentation
|
2020-03-10 20:54:42 -06:00 |
|
tangxifan
|
0da6f00af5
|
start reworking the openfpga tool documentation
|
2020-03-10 17:29:35 -06:00 |
|
tangxifan
|
089cc5e86e
|
update documentation on circuit model annotation on VPR architecture
|
2020-03-10 16:51:50 -06:00 |
|
tangxifan
|
7195564455
|
reworked circuit model examples in documentation. Now we are consistent to latest syntax
|
2020-03-10 16:17:20 -06:00 |
|
tangxifan
|
54dfdc0cc1
|
update general documentation on circuit library
|
2020-03-10 12:18:12 -06:00 |
|
tangxifan
|
2a3c5b98a5
|
minor format fix in documentation
|
2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
|
d14fa16905
|
finish documentation update on technology library
|
2020-03-09 21:17:25 -06:00 |
|
Xifan Tang
|
cb7e4a1dfa
|
finish documentation the simulation settings in VPR8 integration
|
2020-03-09 20:03:37 -06:00 |
|
tangxifan
|
751735bf41
|
update documentation in simulation setting syntax
|
2020-03-09 17:40:33 -06:00 |
|
tangxifan
|
3c7fd30e12
|
merged tutorial to online documentation and reworked compilation guidelines
|
2020-03-09 13:58:24 -06:00 |
|
tangxifan
|
af6319a6b0
|
reworked motivation in documentation
|
2020-03-09 11:27:25 -06:00 |
|
tangxifan
|
73da4a1d6e
|
rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
|
2020-03-09 10:32:03 -06:00 |
|
tangxifan
|
f821e60405
|
clean up deadlinks in doc
|
2020-03-09 10:15:16 -06:00 |
|
tangxifan
|
d61ae5561b
|
start cleanup the documentation for openfpga shell
|
2020-03-09 09:44:19 -06:00 |
|
tangxifan
|
f67981afa8
|
update ducoumentation to explain lib_name XML syntax
|
2020-01-08 14:22:17 -07:00 |
|
tangxifan
|
13f964ea72
|
add bitstream file format introduction
|
2019-12-04 13:41:31 -07:00 |
|
tangxifan
|
40bddd4ed7
|
add FPL'19 paper to documentation reference
|
2019-12-04 12:05:30 -07:00 |
|
tangxifan
|
323c4fdc9a
|
clean up documentation build warnings and add guidelines for port naming
|
2019-12-04 11:59:10 -07:00 |
AurelienUoU
|
36f7624b95
|
Point to point truth table typo fix
|
2019-10-01 13:07:27 -06:00 |
|
AurelienUoU
|
e2867019e1
|
Typo fixing
|
2019-09-30 10:38:02 -06:00 |
|
AurelienUoU
|
74f7a3cfb2
|
Doc fixing
|
2019-09-30 10:29:42 -06:00 |
|
AurelienUoU
|
5ac79f4805
|
Point to point documentation
|
2019-09-30 10:00:46 -06:00 |
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
32d47d6b8b
|
Update document + Travis cache check
|
2019-08-31 16:13:47 -06:00 |
|
Ganesh Gore
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06c0dbb328
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Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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c4180fad6d
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Added .gitignore to build docs locally
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2019-08-25 00:49:04 -06:00 |
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tangxifan
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42b528be57
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doc updates
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2019-08-21 15:11:25 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
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Xifan Tang
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afd78604c9
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Merge branch 'dev' into documentation: resolved conflicts and add logo files
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2019-07-17 17:50:11 -04:00 |
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Xifan Tang
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e7b40f06b0
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Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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AurelienUoU
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df53f6da2c
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Updates FPGA-Verilog command lines
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2019-07-05 13:41:34 -06:00 |
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AurelienUoU
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9e99048815
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Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
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2019-07-05 11:56:02 -06:00 |
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AurelienUoU
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27dbc527a0
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Update Readme
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2019-07-05 11:06:55 -06:00 |
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AurelienUoU
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f56adc6815
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Update documentation
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2019-07-05 10:20:16 -06:00 |
BaudouinChauviere
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cb34ac0243
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Update sc_flow.rst
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2019-04-01 16:30:31 -06:00 |
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BaudouinChauviere
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361bbc13e3
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Update func_verify.rst
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2019-04-01 16:29:42 -06:00 |
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BaudouinChauviere
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a176bf3a19
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Update file_organization.rst
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2019-04-01 16:28:48 -06:00 |
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BaudouinChauviere
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01371ce54d
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Update customize_subckt.rst
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2019-04-01 16:27:06 -06:00 |
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BaudouinChauviere
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1ea7ec3265
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Update spice_simulation.rst
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2019-04-01 16:26:02 -06:00 |
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BaudouinChauviere
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cfdc072164
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Update file_organization.rst
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2019-04-01 16:25:09 -06:00 |
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BaudouinChauviere
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fcc3bf0967
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Update command_line_usage.rst
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2019-04-01 16:23:24 -06:00 |
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BaudouinChauviere
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f4b72bd4e1
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Update link_circuit_modules.rst
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2019-04-01 16:21:59 -06:00 |
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BaudouinChauviere
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ce300c196c
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Update circuit_modules.rst
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2019-04-01 16:13:23 -06:00 |
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BaudouinChauviere
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6e065ef3b3
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Update tech_lib.rst
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2019-04-01 16:09:31 -06:00 |
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BaudouinChauviere
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aed779ca3d
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Update spice_sim_setting.rst
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2019-04-01 16:08:00 -06:00 |
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BaudouinChauviere
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4900caaed9
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Update generality.rst
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2019-04-01 16:04:17 -06:00 |
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BaudouinChauviere
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33df25366c
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Update eda_flow.rst
Correction fix
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2019-04-01 16:02:47 -06:00 |
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BaudouinChauviere
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d6261f1f59
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Update motivation.rst
Typo and better explanations correction
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2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
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39f7b0b9a2
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Update of the doc for better fit with the current version
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2019-04-01 11:55:28 -06:00 |
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BaudouinChauviere
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5dbcfa6d70
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Repair broken link
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2019-01-03 18:26:30 +01:00 |
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BaudouinChauviere
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28010f6c91
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Testing another link method
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2019-01-03 18:24:06 +01:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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30f2ada557
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Repaired broken links
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2019-01-03 18:18:03 +01:00 |
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LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
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Further resizing
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2018-12-29 01:44:24 +01:00 |
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LNIS-Projects
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38a3b01520
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Resize the images
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2018-12-29 01:42:43 +01:00 |
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Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
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2018-12-29 01:14:26 +01:00 |
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Baudouin Chauviere
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0a5391c14f
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Addition of some illustrations
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2018-12-26 18:16:16 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c0626e9a1c
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Adding the Verification Step from ModelSim
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2018-12-26 18:00:03 +01:00 |
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LNIS-Projects
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c506e16d33
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Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
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Update file_organization.rst
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2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
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2018-12-22 14:39:51 +01:00 |
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LNIS-Projects
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55459f7906
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Update index.rst
Reorganization
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2018-12-10 13:46:38 -07:00 |
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LNIS-Projects
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56555fc8a0
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Update index.rst
Removed abc from the project because included in Yosys
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2018-12-10 13:46:02 -07:00 |
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BaudouinChauviere
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88af64c606
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Update eda_flow.rst
Distributions compilable added
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2018-12-05 16:29:07 -07:00 |
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BaudouinChauviere
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576feb600f
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Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
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2018-12-05 16:24:03 -07:00 |
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BaudouinChauviere
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0f87fb9c3f
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Update file_organization.rst
Correction on the routing
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2018-12-03 14:21:40 -07:00 |
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BaudouinChauviere
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e541834bd0
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Update file_organization.rst
Made similar to the SPICE one
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2018-12-03 14:20:34 -07:00 |
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BaudouinChauviere
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cd301a5bb8
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Update file_organization.rst
Correction of the hierarchy
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2018-12-03 14:09:11 -07:00 |
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BaudouinChauviere
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9c97125b0d
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Update spice_simulation.rst
typo
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2018-12-03 13:42:45 -07:00 |
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BaudouinChauviere
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b8f702e16d
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Update file_organization.rst
Creation of the table for better understanding
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2018-12-03 13:40:42 -07:00 |
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BaudouinChauviere
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10cbd2efef
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Update index.rst
Commenting the multi mode out until more mature
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2018-12-03 11:50:13 -07:00 |
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BaudouinChauviere
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8e7def7f88
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Update link_circuit_modules.rst
Correction of typos
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2018-12-03 11:39:44 -07:00 |
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BaudouinChauviere
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f8e801b9d1
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Merge pull request #1 from LNIS-Projects/Documentation-Update
Update index.rst
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2018-12-03 11:27:05 -07:00 |
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BaudouinChauviere
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a4d29aeb1b
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Update circuit_model_examples.rst
Typo correction
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2018-12-03 11:26:04 -07:00 |
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BaudouinChauviere
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e39e0219e9
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Update circuit_modules.rst
Move the examples from this part to their own
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2018-12-03 10:59:20 -07:00 |
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BaudouinChauviere
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7a49ca8ce2
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Update index.rst
New section in the doc
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2018-12-03 10:58:50 -07:00 |
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BaudouinChauviere
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99769c1510
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Create circuit_model_examples.rst
Better architecture of the doc
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2018-12-03 10:58:11 -07:00 |
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BaudouinChauviere
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47a214520f
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Update index.rst
Skip lines
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2018-12-03 10:32:15 -07:00 |
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BaudouinChauviere
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6827549be2
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Update index.rst
Include the links for the external documentation
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2018-12-03 10:31:02 -07:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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aa5449c37d
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Verif_modif_doc_title_2
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2018-10-17 16:49:55 -06:00 |
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Aurelien Alacchi
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6327a4486b
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Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
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2018-10-17 16:47:32 -06:00 |
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Aurelien Alacchi
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8f7f88ebea
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Verif_modif_doc_title
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2018-10-17 16:45:42 -06:00 |
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Aurelien Alacchi
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2cfbe2b997
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FPGA-Verilog_doc_update
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2018-10-17 16:38:03 -06:00 |
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Aurelien Alacchi
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e96c6e2f02
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Revert "Bug_correction_fpga-spice_commandLine"
This reverts commit 33e76d0255.
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2018-10-12 16:09:14 -06:00 |
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Aurelien Alacchi
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33e76d0255
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Bug_correction_fpga-spice_commandLine
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2018-10-12 16:05:53 -06:00 |
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Aurelien Alacchi
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26538cb2bc
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Correction_file_commandline_fpga-spice
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2018-10-12 16:03:23 -06:00 |
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Aurelien Alacchi
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e0c2fc2c8a
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Documentation_code&example_update
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2018-10-12 15:50:09 -06:00 |
Aurelien Alacchi
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07380ed1fa
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Minor_bug_fig_name_correction
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2018-10-09 15:33:30 -06:00 |
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Aurelien Alacchi
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a43574e593
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Update_doc_circuit_level_fig_fixed
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2018-10-09 15:29:15 -06:00 |
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Aurelien Alacchi
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d1c01cd68b
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Update_bug_fig_doc_CL
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2018-10-08 17:54:44 -06:00 |
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Aurelien Alacchi
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7c51129a33
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test42docFig
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2018-10-08 16:20:34 -06:00 |
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Aurelien Alacchi
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8723722e99
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test_correction_bug_fig_doc_CL
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2018-10-08 16:18:56 -06:00 |
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Aurelien Alacchi
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ebd4b282f5
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test_correction_figure
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2018-10-08 16:00:21 -06:00 |
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Aurelien Alacchi
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a318f8e20e
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Update_doc_circuit_level_bug_image
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2018-10-08 15:48:54 -06:00 |
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Aurelien Alacchi
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f79913f379
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Update_doc_circuit_level_bug_image
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2018-10-08 15:42:19 -06:00 |
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Aurelien Alacchi
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44bdca0429
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Revert "figure_correction_doc_circuit_level"
This reverts commit 046829bd13.
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2018-10-08 15:30:47 -06:00 |
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Aurelien Alacchi
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054a2bb186
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Revert "bug_correction_fig_circuit_level"
This reverts commit c6cd63462c.
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2018-10-08 15:30:36 -06:00 |
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Aurelien Alacchi
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c6cd63462c
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bug_correction_fig_circuit_level
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2018-10-08 15:30:03 -06:00 |
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Aurelien Alacchi
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046829bd13
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figure_correction_doc_circuit_level
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2018-10-08 15:27:30 -06:00 |
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Aurelien Alacchi
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cf1dddff5f
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-10-08 15:19:48 -06:00 |
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Aurelien Alacchi
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cf804b8fb2
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Define Circuit Level update
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2018-10-08 15:15:44 -06:00 |
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LNIS-Projects
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05f70548f3
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Add files via upload
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2018-10-08 15:02:16 -06:00 |
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Baudouin Chauviere
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16c0c4656e
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Adds titles and WiP tags for new parts. Tutorials included
Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
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2018-09-25 14:53:04 -06:00 |
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Baudouin Chauviere
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70d303dfb5
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Define Circuit doc improvement
Added some content, better spacing for understanding and made some changes in the options we show
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2018-09-25 11:53:53 -06:00 |
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tangxifan
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f47246e8b7
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Fixed doc ref problem
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2018-09-14 14:02:47 -06:00 |
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tangxifan
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087ba475bb
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debugging bibtex
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2018-09-14 13:58:20 -06:00 |
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tangxifan
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965835debe
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debugging doc ref
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2018-09-14 13:48:57 -06:00 |
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tangxifan
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4afbce10a3
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fixing bugs for doc references
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2018-09-14 13:44:40 -06:00 |
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tangxifan
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5d697da4e7
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refine doc hierarchy
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2018-09-14 13:27:05 -06:00 |
唐希凡
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0bfbc9b0aa
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update docs
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2018-09-14 13:11:51 -06:00 |
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Xifan Tang
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44e63ec98b
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Test new template
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2018-09-13 23:00:56 -06:00 |
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Xifan Tang
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fec0daa2a8
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Update a draft
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2018-09-13 22:58:54 -06:00 |
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唐希凡
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0f31d51c1a
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update doc html template
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2018-09-13 17:59:53 -06:00 |
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唐希凡
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655baa3cd9
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Debugged Doc
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2018-09-13 17:39:57 -06:00 |
Xifan Tang
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cea41801da
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updating documentation
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2018-09-13 16:25:24 -06:00 |
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Xifan Tang
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c94cc01c83
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debugging documentation
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2018-09-13 15:52:08 -06:00 |
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Xifan Tang
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7261a53f3c
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update docs theme
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2018-09-13 15:48:10 -06:00 |
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Xifan Tang
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d6d6951496
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Adding documentation
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2018-09-13 15:38:41 -06:00 |