Update of the doc for better fit with the current version

abc_with_bb_support/Makefile

@@ -24,11 +24,17 @@ MODULES := src/base/abc src/base/abci src/base/cmd \
 	src/sat/bsat src/sat/csat src/sat/msat src/sat/fraig \
 	src/phys/place 	
 
+CC_VERSION := $(shell echo $(CC) | sed 's/gcc-//g')
+#GCC_VERSION := $(shell gcc --version | grep ^gcc | sed 's/^.* //g')
+#GCC_MAJOR := $(shell echo $(GCC_VERSION) | cut -d'.' -f1)
+#GCC_MINOR := $(shell echo $(GCC_VERSION) | cut -d'.' -f2)
+#GCC_VERSION := $(GCC_MAJOR).$(GCC_MINOR)
+
+#ifeq ($(filter $(GCC_VERSION) $(CC_VERSION),4.9),)
+ifeq ($(CC_VERSION),4.9)
+  
 default: $(PROG)
 
-$(info ###################################)
-$(info gcc-4.9 is necessary to compile abc)
-$(info ###################################)
 #OPTFLAGS  := -DNDEBUG -O3
 OPTFLAGS  := -g -O
 
@@ -82,4 +88,9 @@ lib$(PROG).a: $(OBJ)
 
 docs:
 	doxygen doxygen.conf
+else
+
+$(error gcc-4.9 is necessary to compile abc)
+
+endif
 

docs/source/eda_flow.rst

@@ -19,5 +19,37 @@ FPGA-Bitstream is the part of the flow in charge of the functional verification
 How to compile
 ==============
 Running the Makefile in the root of the released package can compile all the source codes. 
-Guides can be found in the *compilation* directory. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could totally work as well, we just did not verify.
-The released package includes a version of VPR with FPGA-SPICE support, Yosys and ACE2.
+Guides can be found in the *compilation* directory in the main folder. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could totally work as well.
+
+As a general rule, the compilation follows these steps:
+
+1) You clone the repository with:
+git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA,git
+
+Two different approaches exist from then on: Either you need the full flow or you just need the extended version of VPR.
+If you need the full flow:
+
+2) Go into the folder you just cloned and make the different submodules through a global Makefile:
+cd OpenFPGA 
+make
+OR 
+make -j 
+(if you have multiple cores. This will make the compilation way faster.) 
+
+If you only need vpr:
+cd OpenFPGA/vpr7_x2p
+make / make -j
+
+3) Architectures, circuits and already written scripts exist to allow you to test the flow without having to provide any new inofrmation to the system. for this:
+cd vpr7_x2p (if not done already)
+cd vpr
+source ./go.sh
+
+go.sh is a script linking to a testing architecture and a simple circuit. The output will be in the folders spice_demo and verilog_demo.
+
+4) If youi only need to see the new options implemented in vpe, do:
+./vpr
+
+This step will show you all the different options which were added on top of VPR to enable deeper analysis of FPGA architectures.
+
+The released package includes a version of VPR with FPGA-SPICE,Verilog and Bitstream support, Yosys and ACE2.

docs/source/fpga_verilog/command_line_usage.rst

@@ -32,7 +32,7 @@ FPGA-Verilog Supported Options::
 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: 
 
 	* **sub_module:** contains each module verilog file and is more detailed in the next part *Verilog Output File Format*. 
-	* **routing:** contains the Verilog routing files. 
+	* **routing:** contains the Verilog for the connection blocks and the switch boxes. 
 	* **lb:** contains the grids Verilog files.
 
 

docs/source/fpga_verilog/sc_flow.rst

@@ -3,7 +3,7 @@ From Verilog to Layout
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.
 
-Contrary to ModelSim, we do not generate yet the scripts in order to directly implement the layout but results are already promising. We succeed in generating the layout for a 10x10 FPGA.
+Because of the commercial nature of the semi-custom design tools we are using,  we cannot share the different scripts that we are using. However, we can show the results to serve as a proof-of-concept and encourage research through it. 
  
 .. _Layout_Diagram:
 

docs/source/index.rst

@@ -41,9 +41,9 @@ Welcome to OpenFPGA's documentation!
    contact
    reference
    
-For more information on the VTR see vtr_doc_ // vtr_github_
+For more information on the VTR see vtr_doc_ or vtr_github_
 
-For more information on the Yosys see yosys_doc_ // yosys_github_
+For more information on the Yosys see yosys_doc_ or yosys_github_
 
 For more information on the original FPGA architecture description language see xml_vtr_
 

docs/source/motivation.rst

@@ -1,6 +1,9 @@
 Motivation
 ==========
 
+FPGA-SPICE
+----------
+
 The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages on generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
 
 It motivates us to develop FPGA-SPICE, an add-on for the current State-of-Art FPGA architecture exploration tools, VPR :cite:`JRose_FPGA_2012`.
@@ -14,3 +17,18 @@ In the appendix, we introduce the hierarchy of the generated SPICE netlists and
 
 The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015`.
 
+FPGA-Verilog
+------------
+
+On a second note, it is becoming more and more necessary to have a fast access to the Verilog code of the structures and architectures researchers want to study. We think that some issues cannot be studies through VPR only and a more complete overview is possible through a more extensive workflow. One of the prerequites for this is the generation of the Verilog which enables Place & Route and Signoff analysis. While VPR enables the researcher to have access to fast results if the characteristics of the system are well known by the user, it is quite limited otherwise. In the same way, it is quite hard to study the same architecture accross multiple technology nodes without strong knowledge of it. 
+
+This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user. 
+
+In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section
+
+FPGA-Bitstream
+--------------
+
+In order to have the right functionality on top of the FPGA generated, it is necessary to have a Bitstream generation which programs the FPGA and gets the right functionality on top of it. For this reason, we generate a Bitstream and some testbenches in parallel which allow the user to do some functional verification of the system. This includes three different testbenches. First, the FPGA is configured then the clock runs with random patterns are generated to test the functionality. Secondly, the FPGA can be configured in parallel to the testbench itself to do a comparison of the signals and check the validity. Finally, the configuration can be skipped to directly have access to the functioning of the system and reduce the processing time.
+
+This will be explained in more depth in the FPGA-Bitstream section.