[Documentation] Update tutorial about tooling

docs/source/tutorials/eda_flow.rst

@@ -1,18 +0,0 @@
-.. _eda_flow:
-
-Supported EDA flows in OpenFPGA
--------------------------------
-
-As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis requires the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in "Tools Guide>Extended Architecture Description Language"). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results when enabled by command-line options. (See each "FPGA-*Branch*" about command-line options available) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See "FPGA-SPICE... > Create Customized SPICE Modules" for guidelines in customizing your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e., HSPICE, can be called to conduct a power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See "FPGA-SPICE... > Run SPICE simulation").
-
-.. _fig_eda_flow:
-
-.. figure:: ./figures/eda_flow.png
-   :scale: 50%
-   :alt: map to buried treasure
-
-   Detailed EDA flows based on FPGA-SPICE/Verilog/Bitstream in the purpose of (a) architecture of the output of FPGA-SPICE (b) functionality verification; (c) prototyping and area analysis and (d) power analysis. *TBD: change for Yosys*
-
-FPGA-Verilog is the part of the flow in charge of the Verilog and the semi-custom design flow. In our case, we use Cadence Innovus. The goal is to get the full-FPGA layout to complete the analysis provided by FPGA-SPICE. By having the layout, we can get an area analysis on the one hand and have new information concerning the power analysis. For instance, having the layout allows the user to have new information on the circuit such as the parasitics. 
-
-FPGA-Bitstream is the part of the flow in charge of the functional verification of the produced FPGA. Testbenches are generated by FPGA-Verilog and are combined with the full FPGA fabric in Modelsim. A bitstream is generated at the same time as the testbenches. This bitstream configures the FPGA with the functionality given by the user to VPR at the beginning of the flow. First, we configure the FPGA with the bitstream, and then waveforms are sent onto the I/O pads to check the functionality.

docs/source/tutorials/index.rst

@@ -6,7 +6,7 @@
 
    compile
 
-   eda_flow
+   tools
 
    design_flow/index
 

docs/source/tutorials/tools.rst

@@ -0,0 +1,47 @@
+.. _openfpga_tools:
+
+Supported Tools
+---------------
+
+Internal Tools
+^^^^^^^^^^^^^^
+
+To enable various design purposes, OpenFPGA integrates several tools to i.e., FPGA-Verilog, FPGA-SDC and FPGA-bitstream (highlighted green in :ref:`fig_openfpga_tools`, with other popular open-source EDA tools, i.e., VPR and Yosys.
+
+.. _fig_openfpga_tools:
+
+.. figure:: figures/openfpga_tools.png
+   :scale: 25%
+   :alt: map to buried treasure
+
+   OpenFPGA tool suites and design flows 
+
+Third-Party Tools
+^^^^^^^^^^^^^^^^^
+
+OpenFPGA accepts and outputs in standard file formats, and therefore can 
+interface a wide range of commercial and open-source tools.
+
++--------------+-------------------------+
+| Usage        | Tools                   |
++==============+=========================+
+| Backend      | Synopsys IC Compiler II |
+|              |                         |
+|              | Cadence Innovus         |
++--------------+-------------------------+
+| Timing       | Synopsys PrimeTime      |
+| Analyzer     |                         |
+|              | Cadence Tempus          |
++--------------+-------------------------+
+| Verification | Synopsys VCS            |
+|              |                         |
+|              | Synopsys Formality      |
+|              |                         |
+|              | Mentor ModelSim         |
+|              |                         |
+|              | Mentor QuestaSim        |
+|              |                         |
+|              | Cadence NCSim           |
+|              |                         |
+|              | Icarus iVerilog         |
++--------------+-------------------------+