renaming design flows in documentation

2020-05-24 23:03:54 -06:00 · 2020-05-24 23:03:54 -06:00 · 35536ee594
parent 011ce5cdf6
commit 35536ee594
2 changed files with 2 additions and 2 deletions
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@ -7,4 +7,4 @@ Design Flows
 .. toctree::
   :maxdepth: 2

-   sc_flow
+   verilog_to_gds2
--- a/docs/source/tutorials/design_flow/verilog_to_gds2.rst
+++ b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
@ -1,4 +1,4 @@
-From Verilog to Layout
+From Verilog to GDSII
 ~~~~~~~~~~~~~~~~~~~~~~

 The generated Verilog code can be used through a semi-custom design flow to generate the layout.