diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index e7e9937ae..610b09b35 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,4 +7,4 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
-   sc_flow
+   verilog_to_gds2
diff --git a/docs/source/tutorials/design_flow/sc_flow.rst b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
similarity index 98%
rename from docs/source/tutorials/design_flow/sc_flow.rst
rename to docs/source/tutorials/design_flow/verilog_to_gds2.rst
index f89d71db2..6efb3041f 100644
--- a/docs/source/tutorials/design_flow/sc_flow.rst
+++ b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
@@ -1,4 +1,4 @@
-From Verilog to Layout
+From Verilog to GDSII
 ~~~~~~~~~~~~~~~~~~~~~~
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.