From 35536ee59428238a08764f430037b0a3b3405585 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 23:03:54 -0600
Subject: [PATCH] renaming design flows in documentation

---
 docs/source/tutorials/design_flow/index.rst                     | 2 +-
 .../tutorials/design_flow/{sc_flow.rst => verilog_to_gds2.rst}  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename docs/source/tutorials/design_flow/{sc_flow.rst => verilog_to_gds2.rst} (98%)

diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index e7e9937ae..610b09b35 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,4 +7,4 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
-   sc_flow
+   verilog_to_gds2
diff --git a/docs/source/tutorials/design_flow/sc_flow.rst b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
similarity index 98%
rename from docs/source/tutorials/design_flow/sc_flow.rst
rename to docs/source/tutorials/design_flow/verilog_to_gds2.rst
index f89d71db2..6efb3041f 100644
--- a/docs/source/tutorials/design_flow/sc_flow.rst
+++ b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
@@ -1,4 +1,4 @@
-From Verilog to Layout
+From Verilog to GDSII
 ~~~~~~~~~~~~~~~~~~~~~~
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.