[Documentation] Update motivation with new set of figures

docs/source/manual/fpga_verilog/testbench.rst

@@ -88,7 +88,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
 .. _fig_preconfig_module:
 
 .. figure:: ./figures/preconfig_module.png
-   :scale: 100%
+   :scale: 25%
 
    Internal structure of a pre-configured FPGA module
 

docs/source/motivation.rst

@@ -27,12 +27,43 @@ The rest of this section will focus on detailed motivation on each of them, as d
 
    Design flows in different purposes using OpenFPGA
 
+Fully Customizable Architecture
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+OpenFPGA supports VPR's architecture description language, which allows 
+users to define versatile programmable fabrics down to point-to-point 
+interconnection.
+OpenFPGA leverage VPR's architecture description by introducing an XML-based 
+architecture annotation, enabling fully customizable FPGA fabric down to 
+circuit elements.
+As illustrated in :ref:`fig_openfpga_arch_lang_coverage`, OpenFPGA's 
+architecture annotation covers a complete FPGA fabric, including both the 
+programmable fabric and the configuration peripheral.
+
+.. _fig_openfpga_arch_lang_coverage:
+
+.. figure:: ./figures/openfpga_arch_lang_coverage.png
+   :scale: 15%
+   :alt: OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation
+
+   OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation
+
+The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
 
 FPGA-Verilog
 ~~~~~~~~~~~~
 
 Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
 computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. 
+FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabling various backend choices, as illustrated in :ref:`fig_fpga_verilog_motivation`.
+
+.. _fig_fpga_verilog_motivation:
+
+.. figure:: ./figures/fpga_verilog_motivation.png
+   :scale: 25%
+   :alt: Flexible netlist format support by FPGA-Verilog to enable various backend choices
+
+   FPGA-Verilog enabling flexible backend flows
 
 The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
 
@@ -41,7 +72,18 @@ FPGA-SDC
 
 Design constraints are indepensible in modern ASIC design flows to guarantee the performance level.
 OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis.
-Our flow automatically generates two sets of SDC files. The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage.
+Our flow automatically generates two sets of SDC files.
+- The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. OpenFPGA allows users to define timing constraints in the architecture description and outputs timing constraints in standard format, enabling fully timing constrained backend flow (see :ref:`fig_fpga_sdc_motivation`).
+- The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage.
+
+.. _fig_fpga_sdc_motivation:
+
+.. figure:: ./figures/fpga_sdc_motivation.png
+   :scale: 25%
+   :alt: FPGA-SDC enabling iterative timing constrained backend flow
+
+   FPGA-SDC enabling iterative timing constrained backend flow
+
 
 The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`.