[Documentation] Update for new options in fpga-verilog

docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst

@@ -29,6 +29,8 @@ write_verilog_testbench
 
   - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
 
+  - ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names.
+
   - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
 
   - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.