update doc for new options

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tangxifan 2020-05-17 19:38:13 -06:00
parent 8915d10d27
commit c2a81c76e1
1 changed files with 2 additions and 0 deletions

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@ -245,6 +245,8 @@ FPGA-SDC
- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
- ``--verbose`` Show verbose log
.. option:: write_analysis_sdc
Write the SDC to run timing analysis for a mapped FPGA fabric