re organize tutorials

docs/source/manual/arch_lang/circuit_library.rst

@@ -339,7 +339,7 @@ These inputs are widely seen in FPGAs, such as clock ports, which are shared bet
 
 The global inouts are short wired across different instances. 
 
-:numref:`fig_global_ioput_ports` shows an example on how the global inouts are wired inside FPGA fabric.
+:numref:`fig_global_inout_ports` shows an example on how the global inouts are wired inside FPGA fabric.
 
 .. _fig_global_inout_ports:
 

docs/source/manual/fpga_verilog/index.rst

@@ -10,7 +10,3 @@ FPGA-Verilog
    fabric_netlist
  
    testbench
-
-   sc_flow
-   
-   

docs/source/tutorials/design_flow/index.rst

@@ -0,0 +1,10 @@
+.. _design_flow_tutorials:
+   Design Flows
+
+Design Flows
+------------
+ 
+.. toctree::
+   :maxdepth: 2
+
+   sc_flow

docs/source/tutorials/index.rst

@@ -7,3 +7,5 @@
    compile
 
    eda_flow
+
+   design_flow/index