update documentation to sync with the new fabric bitstream format
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@ -67,26 +67,13 @@ In principle, the file consist a number of XML node ``<bit>``, each bit contains
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- ``value``: The configuration bit value.
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- ``hierarchy`` represents the location of this block in FPGA fabric.
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The hierachy includes the full hierarchy of this block
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- ``instance`` denotes the instance name which you can find in the fabric netlists
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- ``level`` denotes the depth of the block in the hierarchy
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- ``width`` denotes the number of configuration bits under the instance. Typically, only leaf instance has this attribute.
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- ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
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A quick example:
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.. code-block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_clb_1__2_"/>
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<instance level="2" name="logical_tile_clb_mode_clb__0"/>
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<instance level="3" width="10" name="mem_fle_9_in_5"/>
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</hierarchy>
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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</bit>
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Other information may depend on the type of configuration procotol.
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@ -101,14 +88,7 @@ Other information may depend on the type of configuration procotol.
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.. code-block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_io_bottom_1__0_"/>
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<instance level="2" name="logical_tile_io_mode_io__0"/>
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<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
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<instance level="4" width="1" name="iopad_sram_blwl_mem"/>
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</hierarchy>
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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<bl address="000000"/>
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<wl address="000000"/>
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</bit>
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@ -121,13 +101,6 @@ Other information may depend on the type of configuration procotol.
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.. code-block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_io_bottom_1__0_"/>
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<instance level="2" name="logical_tile_io_mode_io__0"/>
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<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
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<instance level="4" width="1" name="iopad_config_latch_mem"/>
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</hierarchy>
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<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
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<frame address="0000000000000000"/>
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</bit>
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