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update doc to fix format problem; add frame_view to doc

This commit is contained in:
tangxifan 2020-07-26 22:39:33 -06:00
parent 177de90822
commit 872a35fc60
2 changed files with 30 additions and 25 deletions
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51
docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
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@ -20,11 +20,11 @@ The information depends on the type of configuration procotol.
.. option:: vanilla
A line consisting of ``0``|``1``
A line consisting of ``0`` | ``1``
.. option:: scan_chain
A line consisting of ``0``|``1``
A line consisting of ``0`` | ``1``
.. option:: memory_bank
@ -34,7 +34,7 @@ The information depends on the type of configuration procotol.
The second line represents the Word-Line address and configuration bit.
For example
.. code_block::
.. code_block:: xml
<bitline_address> <bit_value>
<wordline_address> <bit_value>
@ -45,10 +45,11 @@ The information depends on the type of configuration procotol.
<wordline_address> <bit_value>
.. option:: frame_based
Multiple lines will be included, each of which is organized as <address><space><bit>.
For example
.. code_block::
.. code_block:: xml
<frame_address> <bit_value>
<frame_address> <bit_value>
@ -98,17 +99,17 @@ Other information may depend on the type of configuration procotol.
.. code_block:: xml
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="iopad_sram_blwl_mem"/>
</hierarchy>
<bl address="000000"/>
<wl address="000000"/>
</bit>
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="iopad_sram_blwl_mem"/>
</hierarchy>
<bl address="000000"/>
<wl address="000000"/>
</bit>
.. option:: frame_based
@ -118,13 +119,13 @@ Other information may depend on the type of configuration procotol.
.. code_block:: xml
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="iopad_config_latch_mem"/>
</hierarchy>
<frame address="0000000000000000"/>
</bit>
<bit id="0" value="1">
<hierarchy>
<instance level="0" name="fpga_top"/>
<instance level="1" name="grid_io_bottom_1__0_"/>
<instance level="2" name="logical_tile_io_mode_io__0"/>
<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
<instance level="4" name="iopad_config_latch_mem"/>
</hierarchy>
<frame address="0000000000000000"/>
</bit>

4
docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
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@ -109,6 +109,10 @@ build_fabric
- ``--write_fabric_key <xml_file>`` Output current fabric key to an XML file
- ``--frame_view`` Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
- ``--verbose`` Show verbose log
.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE