clean up deadlinks in doc

docs/source/contact.rst

@@ -1,15 +1,15 @@
 .. _contact:
-   
+
 Contact
 =======
-
+   
 General questions:
 
 Prof. Pierre-Emmanuel Gaillardon 
 
 pierre-emmanuel.gaillardon@utah.edu
 
-Technical Details about FPGA-SPICE/Verilog/Bitstream:
+Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
 
 Dr. Xifan Tang
 

docs/source/fpga_verilog/file_organization.rst

@@ -1,5 +1,5 @@
 Hierarchy of Verilog Output Files
-============================
+=================================
 
 All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
 

docs/source/fpga_verilog/func_verify.rst

@@ -7,6 +7,6 @@ The point of the verification step is to check that the FPGA reproduces the righ
 
 .. _fig_ModelSim:
 
-.. figure:: ./figures/Verification_step.pdf
-   :scale: 100%
+.. figure:: figures/verification_step.png
+   :scale: 50%
    :alt: Functional Verification using ModelSim

docs/source/tutorials/getting_started.rtf

@@ -1,11 +0,0 @@
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-
-\f0\fs24 \cf0 01 Getting Started\
-=================================================\
-\
-**Under Construction**}