diff --git a/docs/source/contact.rst b/docs/source/contact.rst
index accebded6..469defe1a 100644
--- a/docs/source/contact.rst
+++ b/docs/source/contact.rst
@@ -1,15 +1,15 @@
 .. _contact:
-   
+
 Contact
 =======
-
+   
 General questions:
 
 Prof. Pierre-Emmanuel Gaillardon 
 
 pierre-emmanuel.gaillardon@utah.edu
 
-Technical Details about FPGA-SPICE/Verilog/Bitstream:
+Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
 
 Dr. Xifan Tang
 
diff --git a/docs/source/fpga_verilog/figures/verification_step.png b/docs/source/fpga_verilog/figures/verification_step.png
new file mode 100644
index 000000000..7512f1029
Binary files /dev/null and b/docs/source/fpga_verilog/figures/verification_step.png differ
diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst
index 59e794422..0c223a822 100644
--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@@ -1,5 +1,5 @@
 Hierarchy of Verilog Output Files
-============================
+=================================
 
 All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
 
diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/fpga_verilog/func_verify.rst
index d28ea0ea1..cbb8af96c 100644
--- a/docs/source/fpga_verilog/func_verify.rst
+++ b/docs/source/fpga_verilog/func_verify.rst
@@ -7,6 +7,6 @@ The point of the verification step is to check that the FPGA reproduces the righ
 
 .. _fig_ModelSim:
 
-.. figure:: ./figures/Verification_step.pdf
-   :scale: 100%
+.. figure:: figures/verification_step.png
+   :scale: 50%
    :alt: Functional Verification using ModelSim
diff --git a/docs/source/tutorials/getting_started.rtf b/docs/source/tutorials/getting_started.rtf
deleted file mode 100644
index f094182ef..000000000
--- a/docs/source/tutorials/getting_started.rtf
+++ /dev/null
@@ -1,11 +0,0 @@
-{\rtf1\ansi\ansicpg1252\cocoartf1561\cocoasubrtf400
-{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
-{\colortbl;\red255\green255\blue255;}
-{\*\expandedcolortbl;;}
-\margl1440\margr1440\vieww10800\viewh8400\viewkind0
-\pard\tx566\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0
-
-\f0\fs24 \cf0 01 Getting Started\
-=================================================\
-\
-**Under Construction**}
\ No newline at end of file