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correction of the name of the figure

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LNIS-Projects 2018-12-29 01:45:45 +01:00 committed by GitHub
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docs/source/fpga_verilog/func_verify.rst
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@ -11,7 +11,7 @@ The point of the verification step is to check that the FPGA reproduces the righ
.. _fig_ModelSim:
.. figure:: ./figures/Verification_Step.pdf
.. figure:: ./figures/Verification_step.pdf
:scale: 100%
:alt: Functional Verification using ModelSim