riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Resize the images

This commit is contained in:
LNIS-Projects 2018-12-29 01:42:43 +01:00 committed by GitHub
parent 9ee50de26a
commit 38a3b01520
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/source/fpga_verilog/sc_flow.rst
View File

@ -8,7 +8,7 @@ Contrary to ModelSim, we do not generate yet the scripts in order to directly im
.. _Layout_Diagram:
.. figure:: ./figures/Layout_Diagram.png
:scale: 100%
:scale: 50%
:alt: Diagram of the Layouting process
:numref:`Layout_Diagram` shows the different steps involved into realizing the layout for any design. CTS stands for Clock Tree Synthesys and PPA stands for Power-Performance-Area. First, we create the floorplan with the different tiles involved in the FPGA i.e. the CLBs and place them. Then the clock tree is generated. Finally the design is routed and the PPA signoff is realized. Coupled with FPGA-SPICE, we get silicon level analysis on the design.
@ -18,7 +18,7 @@ In :numref:`Layout_Floorplan`, we show the result we get from the floorplanning
.. _Layout_Floorplan:
.. figure:: ./figures/fpga_asap_10x10_floorplan.png
:scale: 100%
:scale: 50%
:alt: Florplan of a 10x10 FPGA