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[Documentation] Update for default circuit model rules

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tangxifan 2020-08-23 14:08:38 -06:00
parent 9c66a35bf6
commit ac8e937a50
1 changed files with 2 additions and 2 deletions
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docs/source/manual/arch_lang/circuit_library.rst
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@ -78,9 +78,9 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci
.. warning:: ``prefix`` may be deprecated soon
.. note:: Multiplexers cannot be user-defined.
.. warning:: Multiplexers cannot be user-defined.
.. note:: For a circuit model type, only one circuit model can be set as default.
.. warning:: For a circuit model type, only one circuit model is allowed to be set as default. If there is only one circuit model defined in a type, it will be considered as the default automatically.
.. note:: If ``<spice_netlist>`` or ``<verilog_netlist>`` are not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.