From ac8e937a504747dd028e5288f8009ab858c150c4 Mon Sep 17 00:00:00 2001 From: tangxifan <tangxifan@gmail.com> Date: Sun, 23 Aug 2020 14:08:38 -0600 Subject: [PATCH] [Documentation] Update for default circuit model rules --- docs/source/manual/arch_lang/circuit_library.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 9fe29a0fa..59e5f055f 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -78,9 +78,9 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci .. warning:: ``prefix`` may be deprecated soon -.. note:: Multiplexers cannot be user-defined. +.. warning:: Multiplexers cannot be user-defined. -.. note:: For a circuit model type, only one circuit model can be set as default. +.. warning:: For a circuit model type, only one circuit model is allowed to be set as default. If there is only one circuit model defined in a type, it will be considered as the default automatically. .. note:: If ``<spice_netlist>`` or ``<verilog_netlist>`` are not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.