[Documentation] Reorganization the overview part by adding technical highlights

docs/source/index.rst

@@ -7,9 +7,10 @@ Welcome to OpenFPGA's documentation!
 ====================================
 
 .. toctree::
-   :caption: Motivation
+   :maxdepth: 2
+   :caption: Overview
 
-   motivation
+   overview/index
 
 .. toctree::
    :maxdepth: 2

docs/source/manual/fpga_verilog/testbench.rst

@@ -5,6 +5,16 @@ Testbench
 
 In this part, we will introduce the hierarchy, dependency and functionality of each Verilog testbench, which are generated to verify a FPGA fabric implemented with an application.
 
++-----------------+---------+----------------+---------------+
+| Testbench Type  | Runtime | Test Vector    | Test Coverage |
++=================+=========+================+===============+
+| Full            | Long    | Random Stimuli | Full fabric   |
++-----------------+---------+----------------+---------------+
+| Formal-oriented | Short   | Random Stimuli | Programmable  |
+|                 |         |      or        | fabric only   |
+|                 |         | Formal Method  |               |
++-----------------+---------+----------------+---------------+
+
 OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented.
 Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a).
 To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.

docs/source/manual/openfpga_shell/launch_openfpga_shell.rst

@@ -11,8 +11,6 @@ To launch OpenFPGA shell, users can choose two modes.
 
   Launch OpenFPGA in interactive mode where users type-in command by command and get runtime results
 
-  .. warning:: Currently OpenFPGA does not support continued lines and comments
-
 .. option::	--file or -f
 
   Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them

docs/source/overview/index.rst

@@ -0,0 +1,9 @@
+.. _overview:
+   Overview
+ 
+.. toctree::
+   :maxdepth: 2
+
+   motivation
+
+   tech_highlights

docs/source/overview/tech_highlights.rst

@@ -0,0 +1,90 @@
+Technical Highlights
+--------------------
+
+The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**)
+
+Supported Circuit Designs
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
++---------------+-----------------+--------------+-------------------------+
+| Circuit Types | Auto-generation | User-Defined | Design Topologies       |
++===============+=================+==============+=========================+
+| Inverter      |     Yes         |   Yes        | - Power-gating          |
++---------------+-----------------+--------------+-------------------------+
+| Buffer        |     Yes         |   Yes        | - Tapered buffers       |
+|               |                 |              | - Power-gating          |
++---------------+-----------------+--------------+-------------------------+
+| AND gate      |     Yes         |   Yes        | - 2-input               |
++---------------+-----------------+--------------+-------------------------+
+| OR gate       |     Yes         |   Yes        | - 2-input               |
++---------------+-----------------+--------------+-------------------------+
+| MUX2 gate     |     Yes         |   Yes        | - 2-input               |
++---------------+-----------------+--------------+-------------------------+
+| Pass gate     |     Yes         |   Yes        | - Transmission gate     |
+|               |                 |              | - Pass transistor       |
++---------------+-----------------+--------------+-------------------------+
+| Look-Up Table |     Yes         |   Yes        | - **Any size**          |
+|               |                 |              | - Single-output LUT     |
+|               |                 |              | - Fracturable LUT       |
+|               |                 |              | - Buffer location       |
++---------------+-----------------+--------------+-------------------------+
+| Routing       |     Yes         |   No         | - **Any size**          |
+| Multiplexer   |                 |              | - Buffer location       |
+|               |                 |              | - One-level structure   |
+|               |                 |              | - Treee structure       |
+|               |                 |              | - Multi-level structure |
+|               |                 |              | - Local encoders        |
+|               |                 |              | - Constant inputs       |
++---------------+-----------------+--------------+-------------------------+
+| Configurable  |     No          | Yes          | - Latch                 | 
+| Memory        |                 |              | - SRAM                  |
+|               |                 |              | - D-type flip-flop      | 
++---------------+-----------------+--------------+-------------------------+
+| Block RAM     | No              | Yes          | - Single-port           |
+|               |                 |              | - Dual-port             |
+|               |                 |              | - Fracturable           |
+|               |                 |              | - **Any size**          |
++---------------+-----------------+--------------+-------------------------+
+| Arithmetic    | No              | Yes          | - **Any size**          |
+| Units         |                 |              | - Multiplier            |
+|               |                 |              | - Adder                 |
++---------------+-----------------+--------------+-------------------------+
+| I/O           | No              | Yes          | - General purpose I/O   |
+|               |                 |              | - Bi-directional buffer |
+|               |                 |              | - AIB                   |
++---------------+-----------------+--------------+-------------------------+
+
+
+* The user defined netlist could come from a standard cell
+
+Supported FPGA Architectures
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+We support most FPGA architectures that VPR can support!
+The following are most commonly seen architectural features:
+
++--------------------+----------------------------------------------+
+| Block Type         | Architecture features                        |
++====================+==============================================+
+| Programmable Block | - Single-mode Configurable Logic Block (CLB) |
+|                    | - Multi-mode Configurable Logic Block (CLB)  |
+|                    | - Single-mode heterogeneous blocks           |
+|                    | - Multi-mode heterogeneous blocks            |
+|                    | - Flexible local routing architecture        |
++--------------------+----------------------------------------------+
+| Routing Block      | - Tileable routing architecture              |
+|                    | - Flexible connectivity                      |
+|                    | - Flexible Switch Block Patterns             |
++--------------------+----------------------------------------------+
+
+Supported Verilog Modeling
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs
+
+- Synthesizable Behavioral Verilog
+
+- Structural Verilog
+
+- Implicit/Explicit port mapping
+