add documentation on the tileable routing and thru channel support
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@ -14,7 +14,28 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
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.. option:: tileable="<bool>"
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Turn on/off tileable routing resource graph generator
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Turn ``on``/``off`` tileable routing resource graph generator.
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Tileable routing architecture can minimize the number of unique modules in FPGA fabric to be physically implemented.
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Technical details can be found in :cite:`XTang_FPT_2019`.
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.. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.
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.. option:: through_channel="<bool>"
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Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.
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By default, it is ``off``.
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.. _fig_thru_channel:
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.. figure:: ./figures/thru_channel.png
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:scale: 80%
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:alt: Impact of through channel
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Impact on routing architecture when through channel in multi-width and multi-height programmable blocks: (a) disabled; (b) enabled.
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.. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
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``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
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@ -1,5 +1,5 @@
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Bitstream Output File Format
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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FPGA-Bitstream can generate two types of bitstreams:
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@ -95,3 +95,12 @@ doi={10.1109/FPL.2019.00065},
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ISSN={1946-147X},
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month={Sep.},}
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@INPROCEEDINGS{XTang_FPT_2019,
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author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},
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booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)},
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title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
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year={2019},
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volume={},
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number={},
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doi={10.1109/ICFPT47387.2019.00039},
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pages={247-250},}
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