add documentation on the tileable routing and thru channel support

This commit is contained in:
Xifan Tang 2020-03-25 16:52:42 -06:00
parent cb6afea07c
commit b4221e94bb
4 changed files with 32 additions and 2 deletions

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@ -14,7 +14,28 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
.. option:: tileable="<bool>"
Turn on/off tileable routing resource graph generator
Turn ``on``/``off`` tileable routing resource graph generator.
Tileable routing architecture can minimize the number of unique modules in FPGA fabric to be physically implemented.
Technical details can be found in :cite:`XTang_FPT_2019`.
.. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.
.. option:: through_channel="<bool>"
Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.
By default, it is ``off``.
.. _fig_thru_channel:
.. figure:: ./figures/thru_channel.png
:scale: 80%
:alt: Impact of through channel
Impact on routing architecture when through channel in multi-width and multi-height programmable blocks: (a) disabled; (b) enabled.
.. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks

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Bitstream Output File Format
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FPGA-Bitstream can generate two types of bitstreams:

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@ -95,3 +95,12 @@ doi={10.1109/FPL.2019.00065},
ISSN={1946-147X},
month={Sep.},}
@INPROCEEDINGS{XTang_FPT_2019,
author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},
booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)},
title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
year={2019},
volume={},
number={},
doi={10.1109/ICFPT47387.2019.00039},
pages={247-250},}