diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
index 7122c9870..3f51e005d 100644
--- a/docs/source/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -14,7 +14,28 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
 
 .. option:: tileable="<bool>"
 
-  Turn on/off tileable routing resource graph generator
+  Turn ``on``/``off`` tileable routing resource graph generator.
+  
+  Tileable routing architecture can minimize the number of unique modules in FPGA fabric to be physically implemented.
+
+  Technical details can be found in :cite:`XTang_FPT_2019`. 
+
+  .. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.
+
+.. option:: through_channel="<bool>"
+  
+  Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.
+  By default, it is ``off``.
+
+  .. _fig_thru_channel:
+  
+  .. figure:: ./figures/thru_channel.png
+     :scale: 80%
+     :alt: Impact of through channel
+  
+     Impact on routing architecture when through channel in multi-width and multi-height programmable blocks: (a) disabled; (b) enabled.
+
+  .. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
 
 ``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
 
diff --git a/docs/source/arch_lang/figures/thru_channel.png b/docs/source/arch_lang/figures/thru_channel.png
new file mode 100644
index 000000000..26ba72ac7
Binary files /dev/null and b/docs/source/arch_lang/figures/thru_channel.png differ
diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst
index d8190ac67..91975fcc7 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@@ -1,5 +1,5 @@
 Bitstream Output File Format
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Bitstream can generate two types of bitstreams:
 
diff --git a/docs/source/z_reference.bib b/docs/source/z_reference.bib
index d087acd7d..3758761f8 100644
--- a/docs/source/z_reference.bib
+++ b/docs/source/z_reference.bib
@@ -95,3 +95,12 @@ doi={10.1109/FPL.2019.00065},
 ISSN={1946-147X},
 month={Sep.},}
 
+@INPROCEEDINGS{XTang_FPT_2019,
+author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},  
+booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)}, 
+title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
+year={2019},
+volume={},
+number={},
+doi={10.1109/ICFPT47387.2019.00039},
+pages={247-250},}