clean-up documentation for a shallow hierarchy

2020-05-23 21:07:44 -06:00 · 2020-05-23 21:07:44 -06:00 · c27d77a418
parent f6895fcc14
commit c27d77a418
60 changed files with 38 additions and 26 deletions
--- a/docs/source/arch_lang/figures/.DS_Store
+++ b/docs/source/arch_lang/figures/.DS_Store
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@ -13,27 +13,15 @@ Welcome to OpenFPGA's documentation!

 .. toctree::
   :maxdepth: 2
-   :caption: Getting Started
+   :caption: Tutorials

   tutorials/index

 .. toctree::
   :maxdepth: 2
-   :caption: Architecture Description Language
+   :caption: User Manual

-   arch_lang/index
-
-.. toctree::
-   :maxdepth: 2
-   :caption: OpenFPGA Tools
-
-   openfpga_shell/index
-
-   fpga_spice/index
-
-   fpga_verilog/index
-
-   fpga_bitstream/index
+   manual/index

 .. toctree::
   :maxdepth: 2
--- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
--- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
--- a/docs/source/manual/arch_lang/circuit_library.rst
+++ b/docs/source/manual/arch_lang/circuit_library.rst
--- a/docs/source/manual/arch_lang/circuit_model_examples.rst
+++ b/docs/source/manual/arch_lang/circuit_model_examples.rst
--- a/docs/source/manual/arch_lang/direct_interconnect.rst
+++ b/docs/source/manual/arch_lang/direct_interconnect.rst
--- a/docs/source/manual/arch_lang/figures/Buffer.png
+++ b/docs/source/manual/arch_lang/figures/Buffer.png
--- a/docs/source/manual/arch_lang/figures/FF.png
+++ b/docs/source/manual/arch_lang/figures/FF.png
--- a/docs/source/manual/arch_lang/figures/Inverter_1.png
+++ b/docs/source/manual/arch_lang/figures/Inverter_1.png
--- a/docs/source/manual/arch_lang/figures/Tapered_inverter.png
+++ b/docs/source/manual/arch_lang/figures/Tapered_inverter.png
--- a/docs/source/manual/arch_lang/figures/ccff_fpga.png
+++ b/docs/source/manual/arch_lang/figures/ccff_fpga.png
--- a/docs/source/manual/arch_lang/figures/global_inout_ports.png
+++ b/docs/source/manual/arch_lang/figures/global_inout_ports.png
--- a/docs/source/manual/arch_lang/figures/global_input_ports.png
+++ b/docs/source/manual/arch_lang/figures/global_input_ports.png
--- a/docs/source/manual/arch_lang/figures/gpin_ports.png
+++ b/docs/source/manual/arch_lang/figures/gpin_ports.png
--- a/docs/source/manual/arch_lang/figures/gpio_ports.png
+++ b/docs/source/manual/arch_lang/figures/gpio_ports.png
--- a/docs/source/manual/arch_lang/figures/gpout_ports.png
+++ b/docs/source/manual/arch_lang/figures/gpout_ports.png
--- a/docs/source/manual/arch_lang/figures/iopad.png
+++ b/docs/source/manual/arch_lang/figures/iopad.png
--- a/docs/source/manual/arch_lang/figures/lut.png
+++ b/docs/source/manual/arch_lang/figures/lut.png
--- a/docs/source/manual/arch_lang/figures/meas_edge.png
+++ b/docs/source/manual/arch_lang/figures/meas_edge.png
--- a/docs/source/manual/arch_lang/figures/mux.png
+++ b/docs/source/manual/arch_lang/figures/mux.png
--- a/docs/source/manual/arch_lang/figures/mux1lvl.png
+++ b/docs/source/manual/arch_lang/figures/mux1lvl.png
--- a/docs/source/manual/arch_lang/figures/pass-gate.png
+++ b/docs/source/manual/arch_lang/figures/pass-gate.png
--- a/docs/source/manual/arch_lang/figures/pass_transistor.png
+++ b/docs/source/manual/arch_lang/figures/pass_transistor.png
--- a/docs/source/manual/arch_lang/figures/point2point_example.png
+++ b/docs/source/manual/arch_lang/figures/point2point_example.png
--- a/docs/source/manual/arch_lang/figures/point2point_truthtable.png
+++ b/docs/source/manual/arch_lang/figures/point2point_truthtable.png
--- a/docs/source/manual/arch_lang/figures/scff.png
+++ b/docs/source/manual/arch_lang/figures/scff.png
--- a/docs/source/manual/arch_lang/figures/sram.png
+++ b/docs/source/manual/arch_lang/figures/sram.png
--- a/docs/source/manual/arch_lang/figures/thru_channel.png
+++ b/docs/source/manual/arch_lang/figures/thru_channel.png
--- a/docs/source/manual/arch_lang/figures/wire.png
+++ b/docs/source/manual/arch_lang/figures/wire.png
--- a/docs/source/manual/arch_lang/generality.rst
+++ b/docs/source/manual/arch_lang/generality.rst
--- a/docs/source/manual/arch_lang/index.rst
+++ b/docs/source/manual/arch_lang/index.rst
@ -1,5 +1,8 @@
+OpenFPGA Architecture Description
+---------------------------------
+
 .. _arch_lang:
-   Extended FPGA Architecture Description Language
+   OpenFPGA Architecture Description
 
 .. toctree::
   :maxdepth: 2
--- a/docs/source/manual/arch_lang/simulation_setting.rst
+++ b/docs/source/manual/arch_lang/simulation_setting.rst
--- a/docs/source/manual/arch_lang/technology_library.rst
+++ b/docs/source/manual/arch_lang/technology_library.rst
--- a/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
+++ b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
--- a/docs/source/manual/fpga_bitstream/generic_bitstream.rst
+++ b/docs/source/manual/fpga_bitstream/generic_bitstream.rst
--- a/docs/source/manual/fpga_bitstream/index.rst
+++ b/docs/source/manual/fpga_bitstream/index.rst
--- a/docs/source/manual/fpga_spice/command_line_usage.rst
+++ b/docs/source/manual/fpga_spice/command_line_usage.rst
--- a/docs/source/manual/fpga_spice/customize_subckt.rst
+++ b/docs/source/manual/fpga_spice/customize_subckt.rst
--- a/docs/source/manual/fpga_spice/file_organization.rst
+++ b/docs/source/manual/fpga_spice/file_organization.rst
--- a/docs/source/manual/fpga_spice/index.rst
+++ b/docs/source/manual/fpga_spice/index.rst
--- a/docs/source/manual/fpga_spice/spice_simulation.rst
+++ b/docs/source/manual/fpga_spice/spice_simulation.rst
--- a/docs/source/manual/fpga_verilog/figures/Layout_Diagram.png
+++ b/docs/source/manual/fpga_verilog/figures/Layout_Diagram.png
--- a/docs/source/manual/fpga_verilog/figures/Verification_step.pdf
+++ b/docs/source/manual/fpga_verilog/figures/Verification_step.pdf
--- a/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png
+++ b/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png
--- a/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
+++ b/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
--- a/docs/source/manual/fpga_verilog/figures/verification_step.png
+++ b/docs/source/manual/fpga_verilog/figures/verification_step.png
--- a/docs/source/manual/fpga_verilog/file_organization.rst
+++ b/docs/source/manual/fpga_verilog/file_organization.rst
--- a/docs/source/manual/fpga_verilog/func_verify.rst
+++ b/docs/source/manual/fpga_verilog/func_verify.rst
--- a/docs/source/manual/fpga_verilog/index.rst
+++ b/docs/source/manual/fpga_verilog/index.rst
--- a/docs/source/manual/fpga_verilog/sc_flow.rst
+++ b/docs/source/manual/fpga_verilog/sc_flow.rst
--- a/docs/source/manual/index.rst
+++ b/docs/source/manual/index.rst
@ -0,0 +1,18 @@
+.. _tools:
+   OpenFPGA tools
+ 
+.. toctree::
+   :maxdepth: 2
+
+   openfpga_flow/index
+
+   arch_lang/index
+
+   openfpga_shell/index
+
+   fpga_spice/index
+
+   fpga_verilog/index
+
+   fpga_bitstream/index
+
--- a/docs/source/manual/openfpga_flow/index.rst
+++ b/docs/source/manual/openfpga_flow/index.rst
@ -0,0 +1,12 @@
+OpenFPGA Flow
+-------------
+
+.. _openfpga_flow:
+   OpenFPGA Flow
+ 
+.. toctree::
+   :maxdepth: 2
+
+   run_fpga_flow
+
+   run_fpga_task
--- a/docs/source/manual/openfpga_flow/run_fpga_flow.rst
+++ b/docs/source/manual/openfpga_flow/run_fpga_flow.rst
--- a/docs/source/manual/openfpga_flow/run_fpga_task.rst
+++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst
--- a/docs/source/manual/openfpga_shell/index.rst
+++ b/docs/source/manual/openfpga_shell/index.rst
--- a/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst
+++ b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst
--- a/docs/source/manual/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst
--- a/docs/source/manual/openfpga_shell/openfpga_script.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_script.rst
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@ -1,5 +1,5 @@
 .. _tutorials:
-   Getting Started
+   Tutorials
 
 .. toctree::
   :maxdepth: 2
@ -7,12 +7,3 @@
   compile

   eda_flow
-
-   run_fpga_flow
-
-   run_fpga_task
-
-   
-  
-
-