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279 Commits

Author SHA1 Message Date
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf 05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf dce1fae777 Added cell->known(), cell->input(portname), cell->output(portname) 2015-02-07 11:40:19 +01:00
Clifford Wolf 5b41470e15 Skip blackbox modules in design->selected_modules() 2015-02-03 23:12:23 +01:00
Clifford Wolf f80f5b721d Added "equiv_make -blacklist <file> -encfile <file>" 2015-01-31 12:08:20 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf abf8398216 Progress in equiv_simple 2015-01-21 23:59:58 +00:00
Clifford Wolf 76c5d863c5 Added equiv_make command 2015-01-19 13:59:08 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf b32ba6f568 Optimizing no-op cell->setPort() 2015-01-17 12:04:40 +01:00
Clifford Wolf e62d838bd4 Removed SigSpec::extend_xx() api 2015-01-01 11:41:52 +01:00
Clifford Wolf 0675098733 added hashlib::mkhash_init 2014-12-30 18:51:24 +01:00
Clifford Wolf ecd64182c5 Added "yosys -X" 2014-12-29 13:33:33 +01:00
Clifford Wolf a2226e5307 Added mkhash_xorshift() 2014-12-29 00:12:36 +01:00
Clifford Wolf 8773fd5897 Added memhasher (yosys -M) 2014-12-28 21:27:51 +01:00
Clifford Wolf f3a97b75c7 Fixed performance bug in object hashing 2014-12-28 19:03:18 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf ec4751e55c Replaced std::unordered_set (nodict) with Yosys::pool 2014-12-26 21:59:41 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf e52d1f9b9a Added new_dict (hashmap.h) and re-enabled code coverage counters 2014-12-26 19:28:52 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 7775d2806f Added IdString::destruct_guard hack 2014-12-11 21:46:36 +01:00
Clifford Wolf 7d6e586df8 Added bool constructors to SigBit and SigSpec 2014-12-08 15:08:02 +01:00
Clifford Wolf bca2442c67 Added module->addDffe() and module->addDffeGate() 2014-12-08 14:59:38 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 468ae92374 Various win32 / vs build fixes 2014-10-17 14:01:47 +02:00
Clifford Wolf 3be5fa053f Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects 2014-10-16 00:54:14 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf 2442eb3832 Fixed monitor notifications for removed cell 2014-09-14 17:04:39 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf dfbd7dd15a Fixed module->addPmux() 2014-08-30 18:17:22 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf b37d70dfd7 Added mod->addGate() methods for new gate types 2014-08-19 14:26:54 +02:00
Clifford Wolf f3326a6421 Improved sig.remove2() performance 2014-08-17 02:16:56 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() 2014-08-14 23:14:47 +02:00
Clifford Wolf 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern 2014-08-14 22:32:18 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf 60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf f99495a895 Added cover() to all SigSpec constructors 2014-07-28 10:52:30 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf 4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs 2014-07-27 14:47:48 +02:00
Clifford Wolf 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cd6574ecf6 Added some missing "const" in rtlil.h 2014-07-26 15:58:22 +02:00
Clifford Wolf 7ac9dc7f6e Added RTLIL::Module::connections() 2014-07-26 15:58:21 +02:00
Clifford Wolf b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) 2014-07-26 14:31:47 +02:00
Clifford Wolf 3719281ed4 Automatically pack SigSpec on copy/assign 2014-07-26 13:59:30 +02:00
Clifford Wolf e75e495c2b Added new RTLIL::Cell port access methods 2014-07-26 12:22:58 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API 2014-07-25 14:23:10 +02:00
Clifford Wolf 7f1789ad1b Fixed typo in cover id 2014-07-25 03:41:53 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf e589289df7 Some improvements in SigSpec packing/unpacking and checking 2014-07-24 15:05:41 +02:00
Clifford Wolf 22ede43b3f Small changes regarding cover() and check() in SigSpec 2014-07-24 04:46:36 +02:00
Clifford Wolf 798f713629 Added support for YOSYS_COVER_FILE env variable 2014-07-24 04:16:32 +02:00
Clifford Wolf 1b0d5fc22d Added cover() calls to RTLIL::SigSpec methods 2014-07-24 03:50:28 +02:00
Clifford Wolf 82fa356037 Added hashing to RTLIL::SigSpec relational and equal operators 2014-07-23 23:58:03 +02:00
Clifford Wolf f368d792fb Disabled RTLIL::SigSpec::check() in release builds 2014-07-23 21:42:44 +02:00
Clifford Wolf 95ac484548 Fixed release build 2014-07-23 21:38:18 +02:00
Clifford Wolf 2a41afb7b2 Added RTLIL::SigSpec::repeat() 2014-07-23 21:34:14 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf 8fd8e4a468 Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized 2014-07-23 20:11:55 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 85db102e13 Replaced RTLIL::SigSpec::operator!=() with inline version 2014-07-23 15:35:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf c61467a32c Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) 2014-07-23 08:59:54 +02:00
Clifford Wolf 115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern 2014-07-22 23:50:21 +02:00
Clifford Wolf fd4cbe6275 SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form 2014-07-22 22:26:30 +02:00
Clifford Wolf a97be0828a Removed RTLIL::SigChunk::compare() 2014-07-22 21:40:52 +02:00
Clifford Wolf 08e1e25169 SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api 2014-07-22 21:33:52 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf 16e5ae0b92 SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 54b0f2e659 Added module->remove(), module->addWire(), module->addCell(), cell->check() 2014-07-21 12:02:55 +02:00
Clifford Wolf e57db5e9b2 Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion 2014-07-20 11:01:04 +02:00
Clifford Wolf 2d69c309f9 Added function-like cell creation helpers 2014-07-18 10:27:06 +02:00
Clifford Wolf 274c514879 Fixed RTLIL::SigSpec::append_bit() for appending constants 2014-07-17 12:10:57 +02:00
Clifford Wolf 73e0e13d2f Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal 2014-07-16 11:38:02 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf d4a1b0af5b Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
Clifford Wolf e164edc8d1 Fixed typo in RTLIL::Module::addAdff() 2014-03-17 14:41:41 +01:00
Clifford Wolf ef1795a1e8 Fixed typo in RTLIL::Module::{addSshl,addSshr} 2014-03-15 22:52:10 +01:00
Clifford Wolf b7c71d92f6 Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API 2014-03-15 14:35:29 +01:00
Clifford Wolf 0ac915a757 Progress in Verific bindings 2014-03-14 11:46:13 +01:00
Clifford Wolf 77e5968323 Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API 2014-03-14 11:45:44 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf 78c64a6401 Fixed a typo in RTLIL::Module::addReduce... 2014-03-10 12:07:26 +01:00
Clifford Wolf fdef064b1d Added RTLIL::Module::add... helper methods 2014-03-10 03:02:27 +01:00
Clifford Wolf 8f9c707a4c Improved checking of internal cell conventions 2014-02-08 19:13:49 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf a1ac710ab8 Stronger checking of internal cells 2014-02-07 17:39:35 +01:00
Clifford Wolf fa295a4528 Added generic RTLIL::SigSpec::parse_sel() with support for selection variables 2014-02-06 19:22:46 +01:00