riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs

This commit is contained in:
Clifford Wolf 2014-07-27 14:47:48 +02:00
parent cbc3a46a97
commit 4be645860b
1 changed files with 26 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
kernel/rtlil.cc
View File

@ -1978,19 +1978,36 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
void RTLIL::SigSpec::remove_const()
{
cover("kernel.rtlil.sigspec.remove_const");
if (packed())
{
cover("kernel.rtlil.sigspec.remove_const.packed");
unpack();
std::vector<RTLIL::SigChunk> new_chunks;
new_chunks.reserve(SIZE(chunks_));
std::vector<RTLIL::SigBit> new_bits;
new_bits.reserve(width_);
width_ = 0;
for (auto &chunk : chunks_)
if (chunk.wire != NULL) {
new_chunks.push_back(chunk);
width_ += chunk.width;
}
for (auto &bit : bits_)
if (bit.wire != NULL)
new_bits.push_back(bit);
chunks_.swap(new_chunks);
}
else
{
cover("kernel.rtlil.sigspec.remove_const.unpacked");
bits_.swap(new_bits);
width_ = bits_.size();
std::vector<RTLIL::SigBit> new_bits;
new_bits.reserve(width_);
for (auto &bit : bits_)
if (bit.wire != NULL)
new_bits.push_back(bit);
bits_.swap(new_bits);
width_ = bits_.size();
}
check();
}