riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed release build

This commit is contained in:
Clifford Wolf 2014-07-23 21:38:18 +02:00
parent 375aa71dfe
commit 95ac484548
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kernel/rtlil.cc
View File

@ -1291,8 +1291,10 @@ RTLIL::Memory::Memory()
void RTLIL::Cell::check()
{
#ifndef NDEBUG
InternalCellChecker checker(NULL, this);
checker.check();
#endif
}
RTLIL::SigChunk::SigChunk()