riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added RTLIL::Module::connections()

This commit is contained in:
Clifford Wolf 2014-07-26 14:38:33 +02:00
parent b03aec6e32
commit 7ac9dc7f6e
2 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
kernel/rtlil.cc
View File

@ -883,6 +883,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs
connections_.push_back(RTLIL::SigSig(lhs, rhs));
}
const std::vector<RTLIL::SigSig> &RTLIL::Module::connections()
{
return connections_;
}
void RTLIL::Module::fixup_ports()
{
std::vector<RTLIL::Wire*> all_ports;

1
kernel/rtlil.h
View File

@ -290,6 +290,7 @@ struct RTLIL::Module
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
const std::vector<RTLIL::SigSig> &connections();
void fixup_ports();
template<typename T> void rewrite_sigspecs(T functor);