riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added SigSpec::has_const()

This commit is contained in:
Clifford Wolf 2015-02-08 00:01:51 +01:00
parent 0da320f151
commit 05d4223fb6
2 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
kernel/rtlil.cc
View File

@ -1078,6 +1078,7 @@ void RTLIL::Module::check()
for (auto &it : connections_) {
log_assert(it.first.size() == it.second.size());
log_assert(!it.first.has_const());
it.first.check();
it.second.check();
}
@ -2968,6 +2969,17 @@ bool RTLIL::SigSpec::is_fully_undef() const
return true;
}
bool RTLIL::SigSpec::has_const() const
{
cover("kernel.rtlil.sigspec.has_const");
pack();
for (auto it = chunks_.begin(); it != chunks_.end(); it++)
if (it->width > 0 && it->wire == NULL)
return true;
return false;
}
bool RTLIL::SigSpec::has_marked_bits() const
{
cover("kernel.rtlil.sigspec.has_marked_bits");

1
kernel/rtlil.h
View File

@ -672,6 +672,7 @@ public:
bool is_fully_const() const;
bool is_fully_def() const;
bool is_fully_undef() const;
bool has_const() const;
bool has_marked_bits() const;
bool as_bool() const;