mirror of https://github.com/YosysHQ/yosys.git
Fixed performance bug in object hashing
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parent
89723a45cf
commit
f3a97b75c7
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@ -236,7 +236,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
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RTLIL::Design::Design()
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{
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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refcount_modules_ = 0;
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@ -450,7 +450,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
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RTLIL::Module::Module()
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{
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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design = nullptr;
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@ -1741,7 +1741,7 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
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RTLIL::Wire::Wire()
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{
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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module = nullptr;
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@ -1755,7 +1755,7 @@ RTLIL::Wire::Wire()
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RTLIL::Memory::Memory()
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{
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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width = 1;
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@ -1764,7 +1764,7 @@ RTLIL::Memory::Memory()
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RTLIL::Cell::Cell() : module(nullptr)
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{
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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}
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@ -712,7 +712,7 @@ struct RTLIL::Monitor
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unsigned int hash() const { return hashidx_; }
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Monitor() {
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unsigned int hashidx_count = 0;
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static unsigned int hashidx_count = 0;
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hashidx_ = hashidx_count++;
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}
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