mirror of https://github.com/YosysHQ/yosys.git
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
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@ -1451,10 +1451,17 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
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RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
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{
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chunks.reserve(bits.size());
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this->width = 0;
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for (auto &bit : bits)
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chunks.push_back(bit);
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this->width = bits.size();
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append_bit(bit);
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check();
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}
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RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
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{
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this->width = 0;
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for (auto &bit : bits)
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append_bit(bit);
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check();
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}
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@ -505,6 +505,7 @@ struct RTLIL::SigSpec {
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SigSpec(RTLIL::State bit, int width = 1);
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SigSpec(RTLIL::SigBit bit, int width = 1);
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SigSpec(std::vector<RTLIL::SigBit> bits);
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SigSpec(std::set<RTLIL::SigBit> bits);
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void expand();
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void optimize();
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RTLIL::SigSpec optimized() const;
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