mirror of https://github.com/YosysHQ/yosys.git
Added RTLIL::ObjIterator and RTLIL::ObjRange
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@ -274,6 +274,12 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me
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return selection_stack.back().selected_member(mod_name, memb_name);
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}
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RTLIL::Module::Module()
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{
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refcount_wires_ = 0;
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refcount_cells_ = 0;
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}
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RTLIL::Module::~Module()
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{
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for (auto it = wires_.begin(); it != wires_.end(); it++)
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@ -772,6 +778,9 @@ void RTLIL::Module::optimize()
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void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
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{
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log_assert(new_mod->refcount_wires_ == 0);
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log_assert(new_mod->refcount_cells_ == 0);
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new_mod->name = name;
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new_mod->connections_ = connections_;
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new_mod->attributes = attributes;
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@ -815,15 +824,17 @@ RTLIL::Module *RTLIL::Module::clone() const
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void RTLIL::Module::add(RTLIL::Wire *wire)
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{
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assert(!wire->name.empty());
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assert(count_id(wire->name) == 0);
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log_assert(!wire->name.empty());
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log_assert(count_id(wire->name) == 0);
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log_assert(refcount_wires_ == 0);
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wires_[wire->name] = wire;
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}
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void RTLIL::Module::add(RTLIL::Cell *cell)
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{
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assert(!cell->name.empty());
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assert(count_id(cell->name) == 0);
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log_assert(!cell->name.empty());
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log_assert(count_id(cell->name) == 0);
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log_assert(refcount_cells_ == 0);
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cells_[cell->name] = cell;
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}
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@ -856,20 +867,24 @@ void RTLIL::Module::remove(RTLIL::Wire *wire)
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void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
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{
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log_assert(refcount_wires_ == 0);
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DeleteWireWorker delete_wire_worker;
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delete_wire_worker.module = this;
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delete_wire_worker.wires_p = &wires;
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rewrite_sigspecs(delete_wire_worker);
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for (auto &it : wires) {
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this->wires_.erase(it->name);
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log_assert(wires_.count(it->name) != 0);
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wires_.erase(it->name);
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delete it;
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}
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}
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void RTLIL::Module::remove(RTLIL::Cell *cell)
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{
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assert(cells_.count(cell->name) != 0);
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log_assert(cells_.count(cell->name) != 0);
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log_assert(refcount_cells_ == 0);
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cells_.erase(cell->name);
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delete cell;
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}
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@ -877,6 +892,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
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void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
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{
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assert(wires_[wire->name] == wire);
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log_assert(refcount_wires_ == 0);
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wires_.erase(wire->name);
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wire->name = new_name;
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add(wire);
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@ -885,6 +901,7 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
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void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
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{
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assert(cells_[cell->name] == cell);
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log_assert(refcount_wires_ == 0);
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cells_.erase(cell->name);
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cell->name = new_name;
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add(cell);
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@ -189,6 +189,86 @@ namespace RTLIL
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RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_bu0 (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().
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// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.
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template<typename T>
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struct ObjIterator
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{
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typename std::map<RTLIL::IdString, T>::iterator it;
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std::map<RTLIL::IdString, T> *list_p;
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int *refcount_p;
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ObjIterator() : list_p(nullptr), refcount_p(nullptr) {
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}
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ObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {
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if (list_p->empty()) {
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this->list_p = nullptr;
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this->refcount_p = nullptr;
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} else {
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it = list_p->begin();
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(*refcount_p)++;
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}
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}
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ObjIterator(const RTLIL::ObjIterator<T> &other) {
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it = other.it;
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list_p = other.list_p;
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refcount_p = other.refcount_p;
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if (refcount_p)
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(*refcount_p)++;
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}
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ObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {
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if (refcount_p)
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(*refcount_p)--;
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it = other.it;
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list_p = other.list_p;
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refcount_p = other.refcount_p;
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if (refcount_p)
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(*refcount_p)++;
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return *this;
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}
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~ObjIterator() {
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if (refcount_p)
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(*refcount_p)--;
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}
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inline T operator*() const {
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assert(list_p != nullptr);
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return it->second;
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}
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inline bool operator!=(const RTLIL::ObjIterator<T> &other) const {
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if (list_p == nullptr || other.list_p == nullptr)
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return list_p != other.list_p;
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return it != other.it;
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}
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inline void operator++() {
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assert(list_p != nullptr);
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if (++it == list_p->end()) {
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(*refcount_p)--;
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list_p = nullptr;
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refcount_p = nullptr;
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}
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}
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};
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template<typename T>
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struct ObjRange
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{
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std::map<RTLIL::IdString, T> *list_p;
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int *refcount_p;
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ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }
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RTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }
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RTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }
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};
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};
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struct RTLIL::Const
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@ -298,6 +378,9 @@ protected:
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void add(RTLIL::Cell *cell);
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public:
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int refcount_wires_;
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int refcount_cells_;
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std::map<RTLIL::IdString, RTLIL::Wire*> wires_;
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std::map<RTLIL::IdString, RTLIL::Cell*> cells_;
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std::vector<RTLIL::SigSig> connections_;
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@ -308,6 +391,7 @@ public:
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std::map<RTLIL::IdString, RTLIL::Process*> processes;
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RTLIL_ATTRIBUTE_MEMBERS
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Module();
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virtual ~Module();
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virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
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virtual size_t count_id(RTLIL::IdString id);
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@ -323,6 +407,9 @@ public:
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void cloneInto(RTLIL::Module *new_mod) const;
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virtual RTLIL::Module *clone() const;
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RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
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RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const std::set<RTLIL::Wire*> &wires);
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void remove(RTLIL::Cell *cell);
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@ -583,7 +670,7 @@ struct RTLIL::SigSpecIterator
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int index;
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inline RTLIL::SigBit &operator*() const;
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inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; }
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inline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }
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inline void operator++() { index++; }
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};
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