riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

This commit is contained in:
Clifford Wolf 2014-07-16 11:38:02 +02:00
parent 964a67ac41
commit 73e0e13d2f
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
kernel/rtlil.cc
View File

@ -619,7 +619,7 @@ namespace {
param_bool("\\CLK_POLARITY");
param("\\PRIORITY");
port("\\CLK", 1);
port("\\EN", 1);
port("\\EN", param("\\WIDTH"));
port("\\ADDR", param("\\ABITS"));
port("\\DATA", param("\\WIDTH"));
check_expected();
@ -639,7 +639,7 @@ namespace {
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
port("\\WR_CLK", param("\\WR_PORTS"));
port("\\WR_EN", param("\\WR_PORTS"));
port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
check_expected();

7
manual/CHAPTER_CellLib.tex
View File

@ -256,8 +256,9 @@ If this parameter is set to {\tt 1'b1}, a read and write to the same address in
return the new value. Otherwise the old value is returned.
\end{itemize}
The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR}
and a data input \B{DATA}. They also have the following parameters:
The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
enable bit for each data bit), an address input \B{ADDR} and a data input
\B{DATA}. They also have the following parameters:
\begin{itemize}
\item \B{MEMID} \\
@ -341,7 +342,7 @@ This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for
This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
\item \B{WR\_EN} \\
This input is \B{WR\_PORTS} bits wide, containing all enable signals for the write ports.
This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
\item \B{WR\_ADDR} \\
This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.