mirror of https://github.com/YosysHQ/yosys.git
Fixed module->addPmux()
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@ -1309,7 +1309,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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cell->parameters["\\WIDTH"] = sig_a.size(); \
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cell->parameters["\\WIDTH"] = sig_b.size(); \
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if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
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cell->setPort("\\A", sig_a); \
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cell->setPort("\\B", sig_b); \
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