mirror of https://github.com/YosysHQ/yosys.git
Added bool constructors to SigBit and SigSpec
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bca2442c67
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@ -2188,6 +2188,16 @@ RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
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check();
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}
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RTLIL::SigSpec::SigSpec(bool bit)
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{
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cover("kernel.rtlil.sigspec.init.bool");
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width_ = 0;
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hash_ = 0;
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append_bit(bit);
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check();
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}
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void RTLIL::SigSpec::pack() const
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{
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RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
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@ -899,6 +899,7 @@ struct RTLIL::SigBit
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SigBit() : wire(NULL), data(RTLIL::State::S0) { }
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SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
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SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { }
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SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
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SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
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SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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@ -982,6 +983,7 @@ public:
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SigSpec(std::vector<RTLIL::SigChunk> chunks);
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SigSpec(std::vector<RTLIL::SigBit> bits);
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SigSpec(std::set<RTLIL::SigBit> bits);
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SigSpec(bool bit);
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SigSpec(RTLIL::SigSpec &&other) {
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width_ = other.width_;
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