mirror of https://github.com/YosysHQ/yosys.git
Improved checking of internal cell conventions
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parent
7f52c18a22
commit
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@ -331,11 +331,20 @@ namespace {
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int param_bool(const char *name)
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{
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int v = param(name);
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if (cell->parameters.at(name).bits.size() > 32)
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error(__LINE__);
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if (v != 0 && v != 1)
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error(__LINE__);
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return v;
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}
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void param_bits(const char *name, int width)
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{
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param(name);
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if (int(cell->parameters.at(name).bits.size()) != width)
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error(__LINE__);
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}
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void port(const char *name, int width)
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{
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if (cell->connections.count(name) == 0)
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@ -541,7 +550,7 @@ namespace {
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if (cell->type == "$adff") {
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param_bool("\\CLK_POLARITY");
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param_bool("\\ARST_POLARITY");
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param("\\ARST_VALUE");
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param_bits("\\ARST_VALUE", param("\\WIDTH"));
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port("\\CLK", 1);
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port("\\ARST", 1);
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port("\\D", param("\\WIDTH"));
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@ -567,9 +576,9 @@ namespace {
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param("\\STATE_NUM");
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param("\\STATE_NUM_LOG2");
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param("\\STATE_RST");
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param("\\STATE_TABLE");
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param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
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param("\\TRANS_NUM");
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param("\\TRANS_TABLE");
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param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
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port("\\CLK", 1);
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port("\\ARST", 1);
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port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
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@ -607,11 +616,11 @@ namespace {
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param("\\MEMID");
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param("\\SIZE");
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param("\\OFFSET");
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param("\\RD_CLK_ENABLE");
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param("\\RD_CLK_POLARITY");
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param("\\RD_TRANSPARENT");
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param("\\WR_CLK_ENABLE");
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param("\\WR_CLK_POLARITY");
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param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
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param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
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param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
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param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
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param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
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port("\\RD_CLK", param("\\RD_PORTS"));
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port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
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port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
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