mirror of https://github.com/YosysHQ/yosys.git
SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
This commit is contained in:
Clifford Wolf
parent
a97be0828a
commit
fd4cbe6275
297
kernel/rtlil.cc
297
kernel/rtlil.cc
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@ -1566,27 +1566,13 @@ RTLIL::SigSpec RTLIL::SigSpec::optimized() const
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void RTLIL::SigSpec::sort()
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{
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pack();
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expand();
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std::sort(chunks_.begin(), chunks_.end());
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optimize();
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unpack();
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std::sort(bits_.begin(), bits_.end());
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}
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void RTLIL::SigSpec::sort_and_unify()
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{
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pack();
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expand();
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std::sort(chunks_.begin(), chunks_.end());
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for (size_t i = 1; i < chunks_.size(); i++) {
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RTLIL::SigChunk &ch1 = chunks_[i-1];
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RTLIL::SigChunk &ch2 = chunks_[i];
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if (ch1 == ch2) {
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chunks_.erase(chunks_.begin()+i);
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width_ -= chunks_[i].width;
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i--;
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}
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}
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optimize();
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*this = this->to_sigbit_set();
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}
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
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@ -1596,36 +1582,26 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
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{
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pack();
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pattern.pack();
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with.pack();
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unpack();
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pattern.unpack();
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with.unpack();
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if (other != NULL)
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other->pack();
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assert(other != NULL);
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assert(width_ == other->width_);
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other->unpack();
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int pos = 0, restart_pos = 0;
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assert(other == NULL || width_ == other->width_);
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for (size_t i = 0; i < chunks_.size(); i++) {
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restart:
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const RTLIL::SigChunk &ch1 = chunks_[i];
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if (chunks_[i].wire != NULL && pos >= restart_pos)
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for (size_t j = 0, poff = 0; j < pattern.chunks_.size(); j++) {
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const RTLIL::SigChunk &ch2 = pattern.chunks_[j];
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assert(ch2.wire != NULL);
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if (ch1.wire == ch2.wire) {
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int lower = std::max(ch1.offset, ch2.offset);
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int upper = std::min(ch1.offset + ch1.width, ch2.offset + ch2.width);
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if (lower < upper) {
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restart_pos = pos+upper-ch1.offset;
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other->replace(pos+lower-ch1.offset, with.extract(poff+lower-ch2.offset, upper-lower));
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goto restart;
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}
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}
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poff += ch2.width;
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}
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pos += chunks_[i].width;
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}
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check();
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assert(pattern.width_ == with.width_);
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std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
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for (int i = 0; i < SIZE(pattern.bits_); i++)
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if (pattern.bits_[i].wire != NULL)
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pattern_map[pattern.bits_[i]] = with.bits_[i];
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for (int i = 0; i < SIZE(bits_); i++)
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if (pattern_map.count(bits_[i]))
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other->bits_[i] = pattern_map.at(bits_[i]);
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other->check();
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}
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void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
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@ -1641,36 +1617,32 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other
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void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
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{
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pack();
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pattern.pack();
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unpack();
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if (other != NULL)
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other->pack();
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int pos = 0;
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assert(other == NULL || width_ == other->width_);
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for (size_t i = 0; i < chunks_.size(); i++) {
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restart:
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const RTLIL::SigChunk &ch1 = chunks_[i];
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if (chunks_[i].wire != NULL)
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for (size_t j = 0; j < pattern.chunks_.size(); j++) {
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const RTLIL::SigChunk &ch2 = pattern.chunks_[j];
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assert(ch2.wire != NULL);
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if (ch1.wire == ch2.wire) {
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int lower = std::max(ch1.offset, ch2.offset);
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int upper = std::min(ch1.offset + ch1.width, ch2.offset + ch2.width);
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if (lower < upper) {
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if (other)
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other->remove(pos+lower-ch1.offset, upper-lower);
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remove(pos+lower-ch1.offset, upper-lower);
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if (i == chunks_.size())
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break;
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goto restart;
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}
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}
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}
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pos += chunks_[i].width;
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if (other != NULL) {
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assert(width_ == other->width_);
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other->unpack();
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}
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std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
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std::vector<RTLIL::SigBit> new_bits, new_other_bits;
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for (int i = 0; i < SIZE(bits_); i++) {
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if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
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continue;
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if (other != NULL)
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new_other_bits.push_back(other->bits_[i]);
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new_bits.push_back(bits_[i]);
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}
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bits_.swap(new_bits);
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width_ = SIZE(bits_);
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if (other != NULL) {
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other->bits_.swap(new_other_bits);
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other->width_ = SIZE(other->bits_);
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}
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check();
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}
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@ -1705,109 +1677,54 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o
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void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
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{
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pack();
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with.pack();
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unpack();
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with.unpack();
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int pos = 0;
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assert(offset >= 0);
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assert(with.width_ >= 0);
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assert(offset+with.width_ <= width_);
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remove(offset, with.width_);
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for (size_t i = 0; i < chunks_.size(); i++) {
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if (pos == offset) {
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chunks_.insert(chunks_.begin()+i, with.chunks_.begin(), with.chunks_.end());
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width_ += with.width_;
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check();
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return;
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}
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pos += chunks_[i].width;
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}
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assert(pos == offset);
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chunks_.insert(chunks_.end(), with.chunks_.begin(), with.chunks_.end());
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width_ += with.width_;
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for (int i = 0; i < with.width_; i++)
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bits_.at(offset + i) = with.bits_.at(i);
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check();
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}
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void RTLIL::SigSpec::remove_const()
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{
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pack();
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for (size_t i = 0; i < chunks_.size(); i++) {
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if (chunks_[i].wire != NULL)
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continue;
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width_ -= chunks_[i].width;
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chunks_.erase(chunks_.begin() + (i--));
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}
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unpack();
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std::vector<RTLIL::SigBit> new_bits;
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new_bits.reserve(width_);
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for (auto &bit : bits_)
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if (bit.wire != NULL)
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new_bits.push_back(bit);
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bits_.swap(new_bits);
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width_ = bits_.size();
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check();
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}
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void RTLIL::SigSpec::remove(int offset, int length)
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{
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pack();
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int pos = 0;
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unpack();
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assert(offset >= 0);
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assert(length >= 0);
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assert(offset+length <= width_);
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for (size_t i = 0; i < chunks_.size(); i++) {
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int orig_width = chunks_[i].width;
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if (pos+chunks_[i].width > offset && pos < offset+length) {
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int off = offset - pos;
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int len = length;
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if (off < 0) {
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len += off;
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off = 0;
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}
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if (len > chunks_[i].width-off)
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len = chunks_[i].width-off;
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RTLIL::SigChunk lsb_chunk = chunks_[i].extract(0, off);
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RTLIL::SigChunk msb_chunk = chunks_[i].extract(off+len, chunks_[i].width-off-len);
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if (lsb_chunk.width == 0 && msb_chunk.width == 0) {
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chunks_.erase(chunks_.begin()+i);
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i--;
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} else if (lsb_chunk.width == 0 && msb_chunk.width != 0) {
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chunks_[i] = msb_chunk;
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} else if (lsb_chunk.width != 0 && msb_chunk.width == 0) {
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chunks_[i] = lsb_chunk;
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} else if (lsb_chunk.width != 0 && msb_chunk.width != 0) {
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chunks_[i] = lsb_chunk;
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chunks_.insert(chunks_.begin()+i+1, msb_chunk);
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i++;
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} else
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assert(0);
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width_ -= len;
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}
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pos += orig_width;
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}
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assert(offset + length <= width_);
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bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
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width_ = bits_.size();
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check();
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}
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RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
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{
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pack();
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int pos = 0;
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RTLIL::SigSpec ret;
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assert(offset >= 0);
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assert(length >= 0);
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assert(offset+length <= width_);
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for (size_t i = 0; i < chunks_.size(); i++) {
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if (pos+chunks_[i].width > offset && pos < offset+length) {
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int off = offset - pos;
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int len = length;
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if (off < 0) {
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len += off;
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off = 0;
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}
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if (len > chunks_[i].width-off)
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len = chunks_[i].width-off;
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ret.chunks_.push_back(chunks_[i].extract(off, len));
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ret.width_ += len;
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offset += len;
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length -= len;
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}
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pos += chunks_[i].width;
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}
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assert(length == 0);
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ret.check();
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return ret;
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unpack();
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return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
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}
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void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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@ -1819,27 +1736,34 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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chunks_.push_back(signal.chunks_[i]);
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width_ += signal.chunks_[i].width;
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}
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// check();
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}
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void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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{
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pack();
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if (chunks_.size() == 0)
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chunks_.push_back(bit);
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else
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if (bit.wire == NULL)
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if (chunks_.back().wire == NULL) {
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chunks_.back().data.bits.push_back(bit.data);
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chunks_.back().width++;
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} else
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chunks_.push_back(bit);
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if (packed())
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{
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if (chunks_.size() == 0)
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chunks_.push_back(bit);
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else
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if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
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chunks_.back().width++;
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if (bit.wire == NULL)
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if (chunks_.back().wire == NULL) {
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chunks_.back().data.bits.push_back(bit.data);
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chunks_.back().width++;
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} else
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chunks_.push_back(bit);
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else
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chunks_.push_back(bit);
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if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
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chunks_.back().width++;
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else
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chunks_.push_back(bit);
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}
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else
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bits_.push_back(bit);
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width_++;
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// check();
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}
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@ -1911,23 +1835,30 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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void RTLIL::SigSpec::check() const
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{
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pack();
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int w = 0;
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for (size_t i = 0; i < chunks_.size(); i++) {
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const RTLIL::SigChunk chunk = chunks_[i];
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if (chunk.wire == NULL) {
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assert(chunk.offset == 0);
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assert(chunk.data.bits.size() == (size_t)chunk.width);
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} else {
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assert(chunk.offset >= 0);
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assert(chunk.width >= 0);
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assert(chunk.offset + chunk.width <= chunk.wire->width);
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assert(chunk.data.bits.size() == 0);
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if (packed())
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{
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int w = 0;
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for (size_t i = 0; i < chunks_.size(); i++) {
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const RTLIL::SigChunk chunk = chunks_[i];
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if (chunk.wire == NULL) {
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assert(chunk.offset == 0);
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assert(chunk.data.bits.size() == (size_t)chunk.width);
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} else {
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assert(chunk.offset >= 0);
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assert(chunk.width >= 0);
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assert(chunk.offset + chunk.width <= chunk.wire->width);
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assert(chunk.data.bits.size() == 0);
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}
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w += chunk.width;
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}
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w += chunk.width;
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assert(w == width_);
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assert(bits_.empty());
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}
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else
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{
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assert(width_ == SIZE(bits_));
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assert(chunks_.empty());
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}
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assert(w == width_);
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}
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bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
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