mirror of https://github.com/YosysHQ/yosys.git
Small changes regarding cover() and check() in SigSpec
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@ -1594,10 +1594,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
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{
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if (other)
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cover("kernel.rtlil.sigspec.replace_other");
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else
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cover("kernel.rtlil.sigspec.replace");
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cover("kernel.rtlil.sigspec.replace");
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unpack();
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pattern.unpack();
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@ -1797,8 +1794,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
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width_ += signal.width_;
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check();
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// check();
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}
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void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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@ -1829,8 +1825,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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}
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width_++;
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check();
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// check();
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}
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void RTLIL::SigSpec::extend(int width, bool is_signed)
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@ -1881,9 +1876,9 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
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return sig;
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}
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#ifndef NDEBUG
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void RTLIL::SigSpec::check() const
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{
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#ifndef NDEBUG
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if (packed())
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{
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cover("kernel.rtlil.sigspec.check.packed");
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@ -1916,8 +1911,8 @@ void RTLIL::SigSpec::check() const
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assert(width_ == SIZE(bits_));
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assert(chunks_.empty());
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}
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#endif
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}
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#endif
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bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
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{
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@ -599,7 +599,11 @@ public:
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operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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#ifndef NDEBUG
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void check() const;
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#else
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inline void check() const { }
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#endif
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};
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inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
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