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1541 Commits

Author SHA1 Message Date
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung a206aed977 Run "opt_expr -fine" instead of "wreduce" due to #1213 2019-08-07 13:59:07 -07:00
Eddie Hung e3d898dccb Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-07 13:44:08 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
David Shah 5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
David Shah a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
David Shah fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
Clifford Wolf 4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Eddie Hung e5be9ff871 Fix spacing 2019-08-06 16:47:55 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
David Shah c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
David Shah 7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Ben Widawsky 7de098ad45 techlibs/intel: Clean up Makefile 
Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-08-05 11:22:11 -07:00
Miodrag Milanovic 8a3329871b clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
Miodrag Milanovic cf96f41c6d Added bram support 2019-08-04 11:46:36 +02:00
Miodrag Milanovic 837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic 6e210f26fa Custom step to add global clock buffers 2019-08-03 14:40:23 +02:00
Miodrag Milanovic ab98f604fd Initial EFINIX support 2019-08-03 13:10:44 +02:00
Clifford Wolf f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Eddie Hung 105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung 65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung 915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung 332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung 7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Eddie Hung d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung 60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung 66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Eddie Hung 2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Clifford Wolf eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf 5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Eddie Hung 5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
David Shah ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Eddie Hung c39ccc65e9 Add copyright header, comment on cascade 2019-07-24 10:49:09 -07:00
Dan Ravensloft 49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Eddie Hung 151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung 4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung 5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung 3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung 47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung 595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung 3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung 1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung 7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah 80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah 79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
Eddie Hung 2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00
David Shah 3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung 171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung 601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung a777be3091 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 20:37:39 -07:00
Eddie Hung 0157043b97 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-18 20:36:48 -07:00
Eddie Hung 15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung 42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung 266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung 2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung 43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
Eddie Hung 8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung 5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
David Shah 9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft 0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
Eddie Hung 2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
Dan Ravensloft 50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Eddie Hung d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
Ben Widawsky 999811572a intel_synth: Fix help message 
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:25 +01:00
Ben Widawsky f950a7a75d intel_synth: Small code cleanup to remove if ladder 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:12 +01:00
Ben Widawsky 809b94a67b intel_synth: Make family explicit and match 
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:03 +01:00
Ben Widawsky 060e77c09b intel_synth: Minor code cleanups 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:05:54 +01:00
Dan Ravensloft c78ab8ebc5 synth_intel: rename for consistency with #1184 
Also fix a typo in the help message.
 2019-07-18 16:46:21 +01:00
Eddie Hung 20b7120d66 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-18 08:11:33 -07:00
Clifford Wolf e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
 2019-07-18 15:34:28 +02:00
David Shah 16b0ccf04c mul2dsp: Lower partial products always have unsigned inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-18 11:33:37 +01:00
Eddie Hung e3f8e59f18 Make all operands signed 2019-07-17 14:25:40 -07:00
Eddie Hung 58e63feae1 Update comment 2019-07-17 13:26:17 -07:00
Eddie Hung 8dca8d486e Fix mul2dsp signedness 2019-07-17 12:44:52 -07:00
Eddie Hung 1b62b82e05 A_SIGNED == B_SIGNED so flip both 2019-07-17 11:34:18 -07:00
David Shah 82153059a1
Merge pull request #1204 from smunaut/fix_1187 
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
 2019-07-17 07:55:26 +01:00
Eddie Hung 0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
Eddie Hung c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Sylvain Munaut f28e38de99 ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-07-16 23:57:15 +02:00
Eddie Hung 6390c535ba Revert drop down to 24x16 multipliers for all 2019-07-16 14:30:25 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung 5d1ce04381 Add support for {A,B,P}REG in DSP48E1 2019-07-16 14:05:50 -07:00
whitequark 698ab9beee synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
whitequark ba099bfe9b synth_{ice40,ecp5}: more sensible pass label naming. 2019-07-16 20:41:51 +00:00
Eddie Hung 7a58ee78dc gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
David Shah d38df68d26 xilinx: Add correct signed behaviour to DSP48E1 model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 17:53:08 +01:00
Eddie Hung ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix 
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
 2019-07-16 08:52:14 -07:00
David Shah 95c8d27b0b xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:47:53 +01:00
David Shah 8da4c1ad82 mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:44:40 +01:00
David Shah 7a75f5f3ac mul2dsp: Fix indentation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:19:32 +01:00
Eddie Hung fd5b3593d8 Do not swap if equals 2019-07-15 16:52:37 -07:00
Eddie Hung 5f00d335d4 Oops forgot these files 2019-07-15 15:03:15 -07:00
Eddie Hung 42f8e68e76 OUT port to Y in generic DSP 2019-07-15 14:45:47 -07:00
Eddie Hung 0c7ee6d0fa Move DSP mapping back out to dsp_map.v 2019-07-15 14:18:44 -07:00
Eddie Hung 5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
Eddie Hung 91fcf034bc Only swap if B_WIDTH > A_WIDTH 2019-07-15 11:24:11 -07:00
Eddie Hung 1793e6018a Tidy up 2019-07-15 11:19:54 -07:00
Eddie Hung 20e3d2d9b0 Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim 2019-07-15 11:13:22 -07:00
Eddie Hung 146451a767 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-15 09:49:41 -07:00
Eddie Hung d032198fac ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT 2019-07-13 01:11:00 -07:00
Clifford Wolf 463f710066
Merge pull request #1183 from whitequark/ice40-always-relut 
synth_ice40: switch -relut to be always on
 2019-07-12 10:48:00 +02:00
Eddie Hung 7a912f22b2 Use Const::from_string() not its constructor... 2019-07-12 01:32:10 -07:00
Eddie Hung 28274dfb09 Off by one 2019-07-12 01:17:53 -07:00
Eddie Hung e0e5d7d68e Fix spacing 2019-07-12 01:15:22 -07:00
Eddie Hung 4de03bd5e6 Remove double push 2019-07-12 01:08:48 -07:00
Eddie Hung 62ac5ebd02 Map to and from this box if -abc9 2019-07-12 00:53:01 -07:00
Eddie Hung 0f5bddcd79 ice40_opt to handle this box and opt back to SB_LUT4 2019-07-12 00:52:31 -07:00
Eddie Hung a79ff2501e Add new box to cells_sim.v 2019-07-12 00:52:19 -07:00
Eddie Hung c6e16e1334 _ABC macro will map and unmap to this new box 2019-07-12 00:51:37 -07:00
Eddie Hung fc3d74616f Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box 2019-07-12 00:50:42 -07:00
Eddie Hung 1c9f3fadb9 Add Tsu offset to boxes, and comments 2019-07-11 17:17:26 -07:00
Eddie Hung d386177e6d ABC doesn't like negative delays in flop boxes... 2019-07-11 17:09:17 -07:00
Eddie Hung 3ef927647c Fix FDCE_1 box 2019-07-11 14:25:47 -07:00
Eddie Hung 1ada568134 Revert "$pastQ should be first input" 
This reverts commit 8f9d529929.
 2019-07-11 14:23:45 -07:00
Eddie Hung 854333f2af Propagate INIT attr 2019-07-11 13:55:47 -07:00
Eddie Hung 8f9d529929 $pastQ should be first input 2019-07-11 13:54:40 -07:00
Eddie Hung 021f8e5492 Fix typo 2019-07-11 13:23:07 -07:00
whitequark b700a4b1c5 synth_ice40: switch -relut to be always on. 2019-07-11 20:18:41 +00:00
whitequark a8c5f7f41e synth_ice40: fix help text typo. NFC. 2019-07-11 20:18:41 +00:00
Eddie Hung 19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram 
synth_xilinx: Initial Spartan 6 block RAM inference support.
 2019-07-11 12:55:35 -07:00
Marcin Kościelnicki a9efacd01d xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
Eddie Hung 8fef4c3594 Simplify to $__ABC_ASYNC box 2019-07-11 10:52:33 -07:00
Eddie Hung 93fbd56db1 $__ABC_FD_ASYNC_MUX.Q -> Y 2019-07-11 10:25:59 -07:00
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Eddie Hung d357431df1 Restore from master 2019-07-10 22:54:39 -07:00
Eddie Hung f984e0cb34 Another typo 2019-07-10 22:33:35 -07:00
Eddie Hung ea6ffea2cd Fix clk_pol for FD*_1 2019-07-10 20:10:20 -07:00
Eddie Hung 7899a06ed6 Another typo 2019-07-10 19:59:24 -07:00
Eddie Hung ad35b509de Another typo 2019-07-10 19:05:53 -07:00
Eddie Hung f3511e4f93 Use \$currQ 2019-07-10 19:01:13 -07:00
Eddie Hung f030be3f1c Preserve all parameters, plus some extra ones for clk/en polarity 2019-07-10 18:57:11 -07:00
Eddie Hung 4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung 3bb48facb2 Remove params from FD*_1 variants 2019-07-10 17:17:54 -07:00
Eddie Hung 0372c900e8 Fix typo, and have !{PRE,CLR} behave as CE 2019-07-10 17:15:49 -07:00
Eddie Hung 7b2599cb94 Move ABC FF stuff to abc_ff.v; add support for other FD* types 2019-07-10 17:06:05 -07:00
Eddie Hung 0ab8f28bc7 Uncomment IS_C_INVERTED parameter 2019-07-10 16:23:15 -07:00
Eddie Hung 838ae1a14c synth_xilinx's map_cells stage to techmap ff_map.v 2019-07-10 16:15:57 -07:00
Eddie Hung 73c8f1a59e Fix box numbering 2019-07-10 16:12:33 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Eddie Hung b33ecd2a74 Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little 2019-07-10 16:00:03 -07:00
Eddie Hung cea7441d8a Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-10 15:58:01 -07:00
Eddie Hung bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime 
Error out if -abc9 and -retime specified
 2019-07-10 14:38:13 -07:00
Eddie Hung 2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux 
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
 2019-07-10 14:38:00 -07:00
Eddie Hung 6bbd286e03 Error out if -abc9 and -retime specified 2019-07-10 12:47:48 -07:00
Eddie Hung 58bb84e5b2 Add some spacing 2019-07-10 12:32:33 -07:00
Eddie Hung 521971e32e Add some ASCII art explaining mux decomposition 2019-07-10 12:20:04 -07:00
Eddie Hung e573d024a2 Call muxpack and pmux2shiftx before cmp2lut 2019-07-09 21:26:38 -07:00
Eddie Hung c55530b901 Restore opt_clean back to original place 2019-07-09 14:29:58 -07:00
Eddie Hung 5b48b18d29 Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 2019-07-09 14:28:54 -07:00
David Shah 27b27b8781 synth_ecp5: Fix typo in copyright header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-09 22:26:10 +01:00
Eddie Hung b1a048a703 Extend using A[1] to preserve don't care 2019-07-09 12:35:41 -07:00
Eddie Hung 93522b0ae1 Extend during mux decomposition with 1'bx 2019-07-09 10:59:37 -07:00
Eddie Hung c864995343 Fix typo and comments 2019-07-09 10:38:07 -07:00
Eddie Hung c91cb73562 Merge remote-tracking branch 'origin/master' into xc7mux 2019-07-09 10:22:49 -07:00
Eddie Hung c68b909210 synth_xilinx to call commands of synth -coarse directly 2019-07-09 10:21:54 -07:00
Eddie Hung 737340327f Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" 
This reverts commit 7f964859ec.
 2019-07-09 10:15:02 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Eddie Hung bc84f7dd10 Fix spacing 2019-07-09 09:22:12 -07:00
Eddie Hung 667199d460 Fix spacing 2019-07-09 09:16:00 -07:00
Clifford Wolf a429aedc0f
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup 
Cleanup synth_xilinx SRL inference, make more consistent
 2019-07-09 16:49:08 +02:00
Eddie Hung 6951e32070 Decompose mux inputs in delay-orientated (rather than area) fashion 2019-07-08 23:51:13 -07:00
Eddie Hung 45da3ada7b Do not call opt -mux_undef (part of -full) before muxcover 2019-07-08 23:49:16 -07:00
Eddie Hung d4ab43d940 Add one more comment 2019-07-08 23:05:48 -07:00
Eddie Hung 939a225f92 Less thinking 2019-07-08 23:02:57 -07:00
Eddie Hung de40453553 Reword 2019-07-08 22:56:19 -07:00
Eddie Hung 7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc 
Add "synth -keepdc" option
 2019-07-08 21:43:16 -07:00
Eddie Hung 7f964859ec synth_xilinx to call "synth -run coarse" with "-keepdc" 2019-07-08 19:23:24 -07:00
Eddie Hung 9ac078be6f Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux 2019-07-08 19:21:53 -07:00
Eddie Hung dd9771cbcd Add synth -keepdc option 2019-07-08 19:14:54 -07:00
Eddie Hung 3f86407cc3 Map $__XILINX_SHIFTX in a more balanced manner 2019-07-08 17:06:35 -07:00
Eddie Hung 78914e2e0e Capitalisation 2019-07-08 17:06:22 -07:00
Eddie Hung baf47e496f Add synth_xilinx -widemux recommended value 2019-07-08 17:04:39 -07:00
Eddie Hung 895ca50173 Fixes for 2:1 muxes 2019-07-08 12:03:38 -07:00
Eddie Hung 0944acf3af synth_xilinx -widemux=2 is minimum now 2019-07-08 11:29:21 -07:00
David Shah c865559f95 xc7: Map combinational DSP48E1s 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 19:15:25 +01:00
Eddie Hung dbe1326573 Parametric muxcover costs as per @daveshah1 2019-07-08 11:08:20 -07:00
Eddie Hung c58998a7d2 atoi -> stoi as per @daveshah1 2019-07-08 10:48:10 -07:00
David Shah e78864993a mul2dsp: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 18:42:41 +01:00
David Shah 269ff450f5 Add mul2dsp multiplier splitting rule and ECP5 mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 18:42:09 +01:00
Dan Ravensloft 4f798cda9d synth_intel: Warn about untested Quartus backend 2019-07-07 19:26:31 +01:00
Eddie Hung 810f8c5dbd Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup 2019-07-02 09:21:02 -07:00
Eddie Hung 2ea6083b7e Fix $__XILINX_MUXF78 box timing 2019-07-01 14:04:06 -07:00
Eddie Hung 09ac274716 Revert "Fix broken MUXFx box, use MUXF7x2 box instead" 
This reverts commit a9a140aa6c.
 2019-07-01 14:01:09 -07:00
Eddie Hung a9a140aa6c Fix broken MUXFx box, use MUXF7x2 box instead 2019-07-01 13:36:27 -07:00
Eddie Hung 5466121ffb Capture all data in one "abc_flop" attribute 2019-07-01 11:50:14 -07:00
Eddie Hung 659c04a68d Update abc_box_id numbering 2019-07-01 10:47:14 -07:00
Eddie Hung 699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Eddie Hung 85f1c2dcbe Cleanup SRL inference/make more consistent 2019-06-29 21:42:20 -07:00
Eddie Hung 62ba724ccb Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-29 19:39:27 -07:00
Eddie Hung dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung 728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Eddie Hung ea0f7c9be9 Restore $__XILINX_MUXF78 const optimisation 2019-06-28 12:12:41 -07:00
Eddie Hung a193bf27c9 Clean up trimming leading 1'bx in A during techmappnig 2019-06-28 12:03:43 -07:00
Eddie Hung cf020befeb Fix CARRY4 abc_box_id 2019-06-28 11:28:50 -07:00
Eddie Hung 4ef26d4755 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:09:42 -07:00
Eddie Hung 03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung 3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung 0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00
Eddie Hung 00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung af8a5ae5fe Extraneous newline 2019-06-27 16:12:20 -07:00
Eddie Hung 4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung 4d00e27ed7 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-27 11:23:30 -07:00
Eddie Hung 1237a4c116 Add warning if synth_xilinx -abc9 with family != xc7 2019-06-27 11:22:49 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung 593e4a30bb MUXF78 -> $__MUXF78 to indicate internal 2019-06-26 20:09:28 -07:00
Eddie Hung dbb8c8caaa Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 20:07:31 -07:00
Eddie Hung 4de25a1949 Add WE to ECP5 dist RAM's abc_scc_break too 2019-06-26 20:02:19 -07:00
Eddie Hung a7a88109f5 Update comment on boxes 2019-06-26 20:00:15 -07:00
Eddie Hung b7bef15b16 Add "WE" to dist RAM's abc_scc_break 2019-06-26 19:58:09 -07:00
Eddie Hung b9ff0503f3 synth_xilinx's muxcover call to be very conservative -- -nodecode 2019-06-26 17:57:10 -07:00
Eddie Hung f0a1726a1a Accidentally removed "simplemap $mux" 2019-06-26 17:48:49 -07:00
Eddie Hung 2b104ed6c8 Replace with <internal options> 2019-06-26 17:42:50 -07:00
Eddie Hung cae69a3edd Rework help_mode for synth_xilinx -widemux 2019-06-26 17:41:21 -07:00
Eddie Hung 5f807a7a5b Return to upstream synth_xilinx with opt -full and wreduce 2019-06-26 16:25:48 -07:00
Eddie Hung 812469aaa3 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 14:48:35 -07:00
Eddie Hung c762be5930 Instead of blocking wreduce on $mux, use -keepdc instead #1132 2019-06-26 11:48:35 -07:00
Eddie Hung 8d8261c71f Do not call opt with -full before muxcover 2019-06-26 11:38:28 -07:00
Eddie Hung 80de03a7a6 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 11:24:39 -07:00
Eddie Hung 4d0014d1b1 Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
Eddie Hung 612083a807 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 10:33:54 -07:00
Eddie Hung 5e1b8d458b Remove unused var 2019-06-26 10:33:07 -07:00
Eddie Hung 988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
Eddie Hung 741ebba70a Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-26 10:10:16 -07:00
Eddie Hung 799b18263f Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:04:01 -07:00
Miodrag Milanovic ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung 4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung 7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Eddie Hung 177c26ca35 Rename -minmuxf to -widemux 2019-06-26 09:16:45 -07:00
Eddie Hung 184cfacfb5 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 09:15:28 -07:00
David Shah 0dd850e655 abc9: Add wire delays to synth_ice40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 11:39:44 +01:00
whitequark 3d4102cfa4 Add more ECP5 Diamond flip-flops. 
This includes all I/O registers, and a few more regular FFs where it
was convenient.
 2019-06-26 01:57:29 +00:00
Eddie Hung 480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung 6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung 4238feed81 This optimisation doesn't seem to work... 2019-06-25 09:21:46 -07:00
Eddie Hung 158325956e Realistic delays for RAM32X1D too 2019-06-24 23:05:28 -07:00
Eddie Hung 3825068a75 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-24 23:04:25 -07:00
Eddie Hung 2f770b7400 Use LUT delays for dist RAM delays 2019-06-24 23:02:53 -07:00
Eddie Hung e1ba25d79f Add RAM32X1D box info 2019-06-24 22:54:35 -07:00
Eddie Hung 1564eb8b54 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-24 22:48:49 -07:00
Eddie Hung 4fadb471a3 Re-enable dist RAM boxes for ECP5 2019-06-24 22:12:50 -07:00
Eddie Hung a4a7e63d84 Revert "Re-enable dist RAM boxes for ECP5" 
This reverts commit ca0225fcfa.
 2019-06-24 22:10:28 -07:00
Eddie Hung ca0225fcfa Re-enable dist RAM boxes for ECP5 2019-06-24 21:55:54 -07:00
Eddie Hung 152e682bd5 Add Xilinx dist RAM as comb boxes 2019-06-24 21:54:01 -07:00
Eddie Hung f1675b88f6 Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux 2019-06-24 16:39:18 -07:00
Eddie Hung efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung c3df895bf4 Reduce MuxFx resources in mux techmapping 2019-06-24 15:16:44 -07:00
Eddie Hung db6a0b72b2 Reduce number of decomposed muxes during techmap 2019-06-24 14:28:56 -07:00
Eddie Hung 2e7992efff Revert "Fix techmapping muxes some more" 
This reverts commit 0aae3b4f43.
 2019-06-24 14:15:31 -07:00
Eddie Hung 7fbfcf20d1 Move comment 2019-06-24 14:15:00 -07:00
Eddie Hung 0aae3b4f43 Fix techmapping muxes some more 2019-06-24 12:50:48 -07:00
Eddie Hung 2b4501503d Fix mux techmapping 2019-06-24 12:18:17 -07:00
Eddie Hung aa1eeda567 Modify costs for muxcover 2019-06-24 11:51:55 -07:00
Eddie Hung 36e6da5396 Change synth_xilinx's -nomux to -minmuxf <int> 2019-06-24 10:04:01 -07:00
Eddie Hung d54dceb547 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-22 19:44:17 -07:00
Eddie Hung 6027549464 Add comments to ecp5 box 2019-06-22 14:33:47 -07:00
Eddie Hung 792d0670c3 Add comment to xc7 box 2019-06-22 14:28:24 -07:00
Eddie Hung 63182ed57d Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
Eddie Hung 7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung 65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung bbf3ad90f5 Remove $_MUX4_ techmap rule 2019-06-21 18:12:33 -07:00
Eddie Hung 39e0e006d5 Fix wreduce call (!!!), tweak muxcover costs 2019-06-21 18:12:07 -07:00
Eddie Hung 6c2cb51996 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-21 17:44:21 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung faa2d6fc1c Constrain wreduce only if wide mux 2019-06-21 17:12:34 -07:00
Eddie Hung aeee9dcad7 Simplify and comment out mux_map.v 2019-06-21 17:06:30 -07:00
Eddie Hung ed00823b41 synth_xilinx to now wreduce except $mux, remove extra peepopt 2019-06-21 16:56:56 -07:00
Eddie Hung 29aee0989f mux_map to no longer copy last value into 1'bx 2019-06-21 16:55:59 -07:00
Eddie Hung 8bce3fb329 Fix spacing 2019-06-21 16:55:34 -07:00
Eddie Hung 694d40719f Fix spacing again, A_forward -> A_backward 2019-06-21 16:47:07 -07:00
Eddie Hung 11886c874c Restore wreduce to synth_xilinx, after muxcover 2019-06-21 16:18:29 -07:00
Eddie Hung 44fc616fc7 Revert B_SIGNED optimisation, since only works for Y_WIDTH==1 2019-06-21 16:18:14 -07:00
Eddie Hung 4d6fac019a Fix spacing 2019-06-21 16:06:13 -07:00
Eddie Hung aa0b107afb synth_xilinx to use _ABC macro, and perform muxpack again 2019-06-21 15:48:20 -07:00
Eddie Hung 9abde12110 Add $__XILINX_MUXF78 to preserve entire box 2019-06-21 15:47:42 -07:00
Eddie Hung 7acbea6b28 Fix alignment 2019-06-21 14:38:30 -07:00
Eddie Hung f433a52374 Add FIXME about need for -mux4 2019-06-21 11:15:23 -07:00
Eddie Hung c6b4653ebe Since muxcover uses MUX4s, blast them back to gates here 2019-06-21 11:13:01 -07:00
Eddie Hung dd22edcd28 Expand synth -coarse without wreduce, move muxcover 2019-06-21 11:12:32 -07:00
David Shah a0d3d2bb41 ecp5: Improve mapping of $alu when BI is used 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 09:45:11 +01:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung f11c9a419b Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 17:38:16 -07:00
Eddie Hung d1dadfcec8 Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 16:45:09 -07:00
Eddie Hung 9faab38e8d mux_map to drop sign bit, and eliminate 'bx-es 2019-06-20 16:45:04 -07:00
Eddie Hung f374e0ab7e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-20 10:18:01 -07:00
acw1251 ce29ede801 Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
acw1251 0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung 4ca847a217 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-18 11:49:54 -07:00
Eddie Hung 8e0a47fb92 Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Eddie Hung 8f5e6d73ff Revert "Fix (do not) permute LUT inputs, but permute mux selects" 
This reverts commit da3d2eedd2.
 2019-06-18 11:35:21 -07:00
Eddie Hung 3d283e69f8 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-18 09:51:28 -07:00
Eddie Hung b304744d15 Clean up 2019-06-18 09:50:37 -07:00
Eddie Hung da3d2eedd2 Fix (do not) permute LUT inputs, but permute mux selects 2019-06-18 09:49:57 -07:00
Eddie Hung 2b0e28b261 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 22:29:34 -07:00
Eddie Hung 608a95eb01 Fix copy-pasta issue 2019-06-17 22:29:22 -07:00
Eddie Hung 59b4e69d16 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 22:25:14 -07:00
Eddie Hung 2a35c4ef94 Permute INIT for +/xilinx/lut_map.v 2019-06-17 22:24:35 -07:00
Eddie Hung 75f8b4cf10 Simplify comment 2019-06-17 19:14:41 -07:00
Eddie Hung 75d92fb590 Merge branch 'xaig' into xaig_dff 2019-06-17 19:11:07 -07:00
Eddie Hung 9d56c0d525 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-17 18:25:35 -07:00
Eddie Hung 840562943f Update LUT7/8 delays to take account for [ABC]OUTMUX delay 2019-06-17 17:06:01 -07:00
Eddie Hung 8a86f9bb62 Add box delays for FD* 2019-06-17 15:13:05 -07:00
Eddie Hung 5ce672d1c5 Merge remote-tracking branch 'origin/xaig' into xaig_dff 2019-06-17 12:14:55 -07:00
Eddie Hung c15ee827f4 Try -W 300 2019-06-17 10:29:06 -07:00
Eddie Hung 1ec450d6bf Try -W 300 2019-06-16 12:08:03 -07:00
Eddie Hung 0c59bc0b75 Cleanup 2019-06-16 10:42:00 -07:00
Eddie Hung d969a9060e Add +/xilinx/abc_ff 2019-06-15 22:41:29 -07:00
Eddie Hung 9ec57b46c2 Fix spacing 2019-06-15 19:36:37 -07:00
Eddie Hung c2f3f116d0 Use $__ABC_FF_ instead of $_FF_ 2019-06-15 18:16:14 -07:00
Eddie Hung 65c7bafc64 Re-order alphabetically 2019-06-15 10:19:05 -07:00
Eddie Hung a76c8a7ffd Fix initialisation of flops 2019-06-15 09:46:35 -07:00
Eddie Hung ac18a76beb Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues 2019-06-15 09:34:48 -07:00
Eddie Hung 295bb23ae0 Wrap FDRE with $__ABC_FDRE containing comb 2019-06-15 09:08:56 -07:00
Eddie Hung 842c110357 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-15 05:48:47 -07:00
Eddie Hung bf312043d4 Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O 2019-06-15 05:45:16 -07:00
Eddie Hung b63b2a0bd4 Revert "Remove wide mux inference" 
This reverts commit 738fdfe8f5.
 2019-06-14 12:50:24 -07:00
Eddie Hung 8fa74287a7 As per @daveshah1 remove async DFF timing from xilinx 2019-06-14 12:43:20 -07:00
Eddie Hung 97d2656375 Resolve comments from @daveshah1 2019-06-14 12:00:02 -07:00
Eddie Hung 2e34859a6b Add XC7_WIRE_DELAY macro to synth_xilinx.cc 2019-06-14 11:38:22 -07:00