mirror of https://github.com/YosysHQ/yosys.git
Add mul2dsp multiplier splitting rule and ECP5 mapping
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
c35023d0bf
commit
269ff450f5
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@ -28,3 +28,4 @@ $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
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$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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@ -0,0 +1,237 @@
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// From Eddie Hung
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// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220
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// revised by Andre DeHon
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// further revised by David Shah
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`ifndef DSP_A_MAXWIDTH
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`define DSP_A_MAXWIDTH 18
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`endif
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`ifndef DSP_A_MAXWIDTH
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`define DSP_B_MAXWIDTH 25
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`endif
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`ifndef ADDER_MINWIDTH
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`define ADDER_MINWIDTH AAA
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`endif
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`ifndef DSP_NAME
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`define DSP_NAME M18x25
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`endif
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`define MAX(a,b) (a > b ? a : b)
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`define MIN(a,b) (a < b ? a : b)
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(* techmap_celltype = "$mul" *)
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module \$mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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generate
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if (A_WIDTH<B_WIDTH) begin
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generate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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.A(A),
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.B(B),
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.Y(Y[Y_WIDTH-1:0])
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);
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endgenerate
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end
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else begin
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generate
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\$__mul_gen #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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.A(B),
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.B(A),
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.Y(Y[Y_WIDTH-1:0])
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);
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endgenerate
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end
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endgenerate
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endmodule
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module \$__mul_gen (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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generate
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if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH;
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localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0);
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wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-2:0];
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
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) mul_slice_first (
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.A(A[`DSP_A_MAXWIDTH-1:0]),
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.B(B),
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.Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
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);
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assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0;
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genvar i;
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generate
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
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) mul_slice (
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.A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]),
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.B(B),
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.Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
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);
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//assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1];
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assign partial_sum[i] = {
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partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]
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+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)],
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partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0]
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};
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end
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endgenerate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH),
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) mul_slice_last (
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.A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]),
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.B(B),
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.Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0])
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);
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//assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2];
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assign Y = {
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partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0]
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+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)],
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partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0]
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};
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH;
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localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0);
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wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-2:0];
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
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) mul_first (
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.A(A),
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.B(B[`DSP_B_MAXWIDTH-1:0]),
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.Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
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);
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assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0;
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genvar i;
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generate
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
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) mul (
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.A(A),
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.B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]),
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.Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
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);
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//assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1];
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// was:
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//assign partial_sum[i] = {
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// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
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// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],
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// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]
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assign partial_sum[i] = {
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partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]
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+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)],
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partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0]
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};
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end
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endgenerate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)
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) mul_last (
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.A(A),
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.B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]),
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.Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0])
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);
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// AMD: this came comment out -- looks closer to right answer
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//assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2];
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// was (looks broken)
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//assign Y = {
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// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
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// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],
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// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]
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assign Y = {
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partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]
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+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)],
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partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0]
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};
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end
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else begin
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wire [A_WIDTH+B_WIDTH-1:0] out;
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wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy;
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wire Asign, Bsign;
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assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
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assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0);
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`DSP_NAME _TECHMAP_REPLACE_ (
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.A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),
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.B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),
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.OUT({dummy, out})
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);
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if (Y_WIDTH < A_WIDTH+B_WIDTH)
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assign Y = out[Y_WIDTH-1:0];
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else begin
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wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0);
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assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };
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end
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end
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endgenerate
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endmodule
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@ -10,6 +10,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
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@ -0,0 +1,10 @@
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
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MULT18X18D mult_i(
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.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
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.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
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.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
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.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
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.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
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);
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endmodule
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@ -89,6 +89,9 @@ struct SynthEcp5Pass : public ScriptPass
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -dsp\n");
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log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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@ -96,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
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}
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string top_opt, blif_file, edif_file, json_file;
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bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
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bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
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void clear_flags() YS_OVERRIDE
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{
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@ -114,6 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
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abc2 = false;
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vpr = false;
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abc9 = false;
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dsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -192,6 +196,10 @@ struct SynthEcp5Pass : public ScriptPass
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abc9 = true;
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continue;
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}
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if (args[argidx] == "-dsp") {
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dsp = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -225,7 +233,28 @@ struct SynthEcp5Pass : public ScriptPass
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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if (dsp) {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
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run("clean");
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run("techmap -map +/ecp5/dsp_map.v");
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}
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run("alumacc");
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run("opt");
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run("fsm");
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run("opt -fast");
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run("memory -nomap");
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run("opt_clean");
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}
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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