mirror of https://github.com/YosysHQ/yosys.git
Capture all data in one "abc_flop" attribute
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@ -23,7 +23,7 @@
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module \$__ABC_FF_ (input C, D, output Q);
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endmodule
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(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
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(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
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module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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