mirror of https://github.com/YosysHQ/yosys.git
Fix signed multiplier decomposition
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5562cb08a4
commit
8326af5418
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@ -5,14 +5,11 @@
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`ifndef DSP_A_MAXWIDTH
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$error("Macro DSP_A_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_A_SIGNEDONLY
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`define DSP_A_SIGNEDONLY 0
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`endif
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`ifndef DSP_B_MAXWIDTH
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$error("Macro DSP_B_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_B_SIGNEDONLY
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`define DSP_B_SIGNEDONLY 0
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`ifndef DSP_SIGNEDONLY
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`define DSP_SIGNEDONLY 0
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`endif
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`ifndef DSP_NAME
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@ -34,7 +31,9 @@ module \$mul (A, B, Y);
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output [Y_WIDTH-1:0] Y;
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generate
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if (`DSP_SIGNEDONLY && !A_SIGNED) begin
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if (A_SIGNED != B_SIGNED)
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wire _TECHMAP_FAIL_ = 1;
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else if (`DSP_SIGNEDONLY && !A_SIGNED) begin
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wire [1:0] dummy;
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\$mul #(
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.A_SIGNED(1),
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@ -98,19 +97,25 @@ module \$__mul_gen (A, B, Y);
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genvar i;
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generate
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if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom);
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localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
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wire [partial_Y_WIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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if (A_SIGNED && B_SIGNED) begin
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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else begin
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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\$__mul_gen #(
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.A_SIGNED(0),
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.B_SIGNED(0),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul_slice_first (
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.A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}),
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.A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}),
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.B(B),
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.Y(partial[0])
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);
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@ -119,7 +124,7 @@ module \$__mul_gen (A, B, Y);
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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.A_SIGNED(0),
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.B_SIGNED(0),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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@ -136,24 +141,26 @@ module \$__mul_gen (A, B, Y);
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul_slice_last (
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.A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
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.A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
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.B(B),
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.Y(partial[n-1])
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);
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assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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assign Y = partial_sum[n-1];
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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`ifdef DSP_B_SIGNEDONLY
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localparam sign_headroom = 1;
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`else
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localparam sign_headroom = 0;
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`endif
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localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom);
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localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);
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wire [partial_Y_WIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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if (A_SIGNED && B_SIGNED) begin
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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else begin
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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wire [Y_WIDTH-1:0] partial_sum [n-1:0];
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end
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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@ -163,7 +170,7 @@ module \$__mul_gen (A, B, Y);
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.Y_WIDTH(partial_Y_WIDTH)
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) mul_first (
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.A(A),
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.B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}),
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.B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}),
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.Y(partial[0])
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);
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assign partial_sum[0] = partial[0];
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@ -180,21 +187,21 @@ module \$__mul_gen (A, B, Y);
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.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),
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.Y(partial[i])
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);
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assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1];
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assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
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end
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)),
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.Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))
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.B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul_last (
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.A(A),
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.B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]),
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.B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
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.Y(partial[n-1])
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);
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assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2];
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assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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end
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else begin
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if (A_SIGNED)
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