mirror of https://github.com/YosysHQ/yosys.git
Use \$currQ
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@ -66,8 +66,13 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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generate
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if (IS_PRE_INVERTED)
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
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else
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
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endgenerate
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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@ -99,7 +104,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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generate
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if (IS_PRE_INVERTED)
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
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@ -117,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, CLR);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
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endmodule
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