mirror of https://github.com/YosysHQ/yosys.git
Add DSP_{A,B}_SIGNEDONLY macro
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@ -3,24 +3,25 @@
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// revised by Andre DeHon
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// further revised by David Shah
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`ifndef DSP_A_MAXWIDTH
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`define DSP_A_MAXWIDTH 18
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$error("Macro DSP_A_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_A_MAXWIDTH
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`define DSP_B_MAXWIDTH 25
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`ifndef DSP_A_SIGNEDONLY
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`define DSP_A_SIGNEDONLY 0
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`endif
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`ifndef ADDER_MINWIDTH
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`define ADDER_MINWIDTH AAA
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`ifndef DSP_B_MAXWIDTH
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$error("Macro DSP_B_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_B_SIGNEDONLY
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`define DSP_B_SIGNEDONLY 0
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`endif
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`ifndef DSP_NAME
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`define DSP_NAME M18x25
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$error("Macro DSP_NAME must be defined");
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`endif
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`define MAX(a,b) (a > b ? a : b)
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`define MIN(a,b) (a < b ? a : b)
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(* techmap_celltype = "$mul" *)
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module \$mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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@ -33,14 +34,42 @@ module \$mul (A, B, Y);
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output [Y_WIDTH-1:0] Y;
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generate
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if (A_WIDTH >= B_WIDTH)
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if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin
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wire dummy;
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\$mul #(
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.A_SIGNED(1),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH+1),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH+1)
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) _TECHMAP_REPLACE_ (
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.A({1'b0, A}),
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.B(B),
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.Y({dummy, Y})
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);
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end
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else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin
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wire dummy;
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\$mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH+1),
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.Y_WIDTH(Y_WIDTH+1)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B({1'b0, B}),
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.Y({dummy, Y})
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);
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end
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else if (A_WIDTH >= B_WIDTH)
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.Y(Y)
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@ -52,7 +81,7 @@ module \$mul (A, B, Y);
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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